mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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90fba37c49
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10137 3c298f89-4303-0410-b956-a3cf2f4a3e73
118 lines
4.3 KiB
C
118 lines
4.3 KiB
C
/*
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* HND SiliconBackplane PCI core hardware definitions.
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*
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* Copyright 2007, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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* $Id$
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*/
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#ifndef _sbpci_h_
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#define _sbpci_h_
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#ifndef _LANGUAGE_ASSEMBLY
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/* cpp contortions to concatenate w/arg prescan */
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#ifndef PAD
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#define _PADLINE(line) pad ## line
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#define _XSTR(line) _PADLINE(line)
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#define PAD _XSTR(__LINE__)
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#endif
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/* Sonics side: PCI core and host control registers */
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typedef struct sbpciregs {
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uint32 control; /* PCI control */
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uint32 PAD[3];
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uint32 arbcontrol; /* PCI arbiter control */
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uint32 PAD[3];
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uint32 intstatus; /* Interrupt status */
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uint32 intmask; /* Interrupt mask */
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uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
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uint32 PAD[9];
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uint32 bcastaddr; /* Sonics broadcast address */
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uint32 bcastdata; /* Sonics broadcast data */
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uint32 PAD[2];
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uint32 gpioin; /* ro: gpio input (>=rev2) */
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uint32 gpioout; /* rw: gpio output (>=rev2) */
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uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
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uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
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uint32 PAD[36];
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uint32 sbtopci0; /* Sonics to PCI translation 0 */
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uint32 sbtopci1; /* Sonics to PCI translation 1 */
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uint32 sbtopci2; /* Sonics to PCI translation 2 */
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uint32 PAD[189];
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uint32 pcicfg[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
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uint16 sprom[36]; /* SPROM shadow Area */
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uint32 PAD[46];
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} sbpciregs_t;
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#endif /* _LANGUAGE_ASSEMBLY */
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/* PCI control */
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#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
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#define PCI_RST 0x02 /* Value driven out to pin */
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#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
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#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
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/* PCI arbiter control */
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#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
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#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
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/* ParkID - for PCI corerev >= 8 */
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#define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */
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#define PCI_PARKID_SHIFT 2
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#define PCI_PARKID_EXT0 0 /* External master 0 */
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#define PCI_PARKID_EXT1 1 /* External master 1 */
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#define PCI_PARKID_EXT2 2 /* External master 2 */
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#define PCI_PARKID_EXT3 3 /* External master 3 (rev >= 11) */
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#define PCI_PARKID_INT 3 /* Internal master (rev < 11) */
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#define PCI11_PARKID_INT 4 /* Internal master (rev >= 11) */
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#define PCI_PARKID_LAST 4 /* Last active master (rev < 11) */
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#define PCI11_PARKID_LAST 5 /* Last active master (rev >= 11) */
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/* Interrupt status/mask */
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#define PCI_INTA 0x01 /* PCI INTA# is asserted */
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#define PCI_INTB 0x02 /* PCI INTB# is asserted */
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#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
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#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
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#define PCI_PME 0x10 /* PCI PME# is asserted */
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/* (General) PCI/SB mailbox interrupts, two bits per pci function */
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#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
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#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
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#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
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#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
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#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
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#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
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#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
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#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
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/* Sonics broadcast address */
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#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
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/* Sonics to PCI translation types */
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#define SBTOPCI0_MASK 0xfc000000
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#define SBTOPCI1_MASK 0xfc000000
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#define SBTOPCI2_MASK 0xc0000000
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#define SBTOPCI_MEM 0
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#define SBTOPCI_IO 1
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#define SBTOPCI_CFG0 2
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#define SBTOPCI_CFG1 3
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#define SBTOPCI_PREF 0x4 /* prefetch enable */
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#define SBTOPCI_BURST 0x8 /* burst enable */
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#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
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#define SBTOPCI_RC_READ 0x00 /* memory read */
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#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
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#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
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/* PCI core index in SROM shadow area */
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#define SRSH_PI_OFFSET 0 /* first word */
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#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
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#define SRSH_PI_SHIFT 12 /* bit 15:12 */
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#endif /* _sbpci_h_ */
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