mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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675367fe81
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@22171 3c298f89-4303-0410-b956-a3cf2f4a3e73
237 lines
6.2 KiB
C
237 lines
6.2 KiB
C
/*
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* Ralink SoC specific GPIO support
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*
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <linux/gpio.h>
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#include <ralink_soc.h>
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#define GPIO0_REG_INT 0x00
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#define GPIO0_REG_EDGE 0x04
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#define GPIO0_REG_RENA 0x08
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#define GPIO0_REG_FENA 0x0c
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#define GPIO0_REG_DATA 0x20
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#define GPIO0_REG_DIR 0x24
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#define GPIO0_REG_POL 0x28
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#define GPIO0_REG_SET 0x2c
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#define GPIO0_REG_RESET 0x30
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#define GPIO0_REG_TOGGLE 0x34
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#define GPIO1_REG_INT 0x38
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#define GPIO1_REG_EDGE 0x3c
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#define GPIO1_REG_RENA 0x40
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#define GPIO1_REG_FENA 0x44
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#define GPIO1_REG_DATA 0x48
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#define GPIO1_REG_DIR 0x4c
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#define GPIO1_REG_POL 0x50
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#define GPIO1_REG_SET 0x54
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#define GPIO1_REG_RESET 0x58
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#define GPIO1_REG_TOGGLE 0x5c
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#define GPIO2_REG_INT 0x60
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#define GPIO2_REG_EDGE 0x64
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#define GPIO2_REG_RENA 0x68
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#define GPIO2_REG_FENA 0x6c
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#define GPIO2_REG_DATA 0x70
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#define GPIO2_REG_DIR 0x74
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#define GPIO2_REG_POL 0x78
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#define GPIO2_REG_SET 0x7c
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#define GPIO2_REG_RESET 0x80
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#define GPIO2_REG_TOGGLE 0x84
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enum ramips_pio_reg {
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RAMIPS_GPIO_REG_INT, /* Interrupt status */
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RAMIPS_GPIO_REG_EDGE,
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RAMIPS_GPIO_REG_RENA,
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RAMIPS_GPIO_REG_FENA,
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RAMIPS_GPIO_REG_DATA,
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RAMIPS_GPIO_REG_DIR, /* Direction, 0:in, 1: out */
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RAMIPS_GPIO_REG_POL, /* Polarity, 0: normal, 1: invert */
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RAMIPS_GPIO_REG_SET,
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RAMIPS_GPIO_REG_RESET,
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RAMIPS_GPIO_REG_TOGGLE,
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RAMIPS_GPIO_REG_MAX
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};
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struct ramips_gpio_chip {
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struct gpio_chip chip;
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spinlock_t lock;
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u8 regs[RAMIPS_GPIO_REG_MAX];
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};
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static void __iomem *ramips_gpio_base;
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static inline struct ramips_gpio_chip *to_ramips_gpio(struct gpio_chip *chip)
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{
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struct ramips_gpio_chip *rg;
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rg = container_of(chip, struct ramips_gpio_chip, chip);
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return rg;
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}
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static inline void ramips_gpio_wr(struct ramips_gpio_chip *rg, u8 reg, u32 val)
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{
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__raw_writel(val, ramips_gpio_base + rg->regs[reg]);
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}
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static inline u32 ramips_gpio_rr(struct ramips_gpio_chip *rg, u8 reg)
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{
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return __raw_readl(ramips_gpio_base + rg->regs[reg]);
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}
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static int ramips_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
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unsigned long flags;
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u32 t;
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spin_lock_irqsave(&rg->lock, flags);
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t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR);
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t &= ~(1 << offset);
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ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t);
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spin_unlock_irqrestore(&rg->lock, flags);
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return 0;
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}
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static int ramips_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
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unsigned long flags;
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u32 reg;
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u32 t;
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reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET;
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spin_lock_irqsave(&rg->lock, flags);
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ramips_gpio_wr(rg, reg, 1 << offset);
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t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR);
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t |= 1 << offset;
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ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t);
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spin_unlock_irqrestore(&rg->lock, flags);
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return 0;
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}
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static void ramips_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
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u32 reg;
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reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET;
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ramips_gpio_wr(rg, reg, 1 << offset);
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}
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static int ramips_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
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u32 t;
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t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DATA);
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return !!(t & (1 << offset));
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}
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static struct ramips_gpio_chip ramips_gpio_chip0 = {
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.chip = {
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.label = "ramips-gpio0",
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.direction_input = ramips_gpio_direction_input,
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.direction_output = ramips_gpio_direction_output,
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.get = ramips_gpio_get,
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.set = ramips_gpio_set,
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.base = 0,
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.ngpio = RALINK_SOC_GPIO0_COUNT,
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},
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.regs = {
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[RAMIPS_GPIO_REG_INT] = GPIO0_REG_INT,
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[RAMIPS_GPIO_REG_EDGE] = GPIO0_REG_EDGE,
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[RAMIPS_GPIO_REG_RENA] = GPIO0_REG_RENA,
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[RAMIPS_GPIO_REG_FENA] = GPIO0_REG_FENA,
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[RAMIPS_GPIO_REG_DATA] = GPIO0_REG_DATA,
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[RAMIPS_GPIO_REG_DIR] = GPIO0_REG_DIR,
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[RAMIPS_GPIO_REG_POL] = GPIO0_REG_POL,
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[RAMIPS_GPIO_REG_SET] = GPIO0_REG_SET,
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[RAMIPS_GPIO_REG_RESET] = GPIO0_REG_RESET,
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[RAMIPS_GPIO_REG_TOGGLE] = GPIO0_REG_TOGGLE,
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},
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};
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static struct ramips_gpio_chip ramips_gpio_chip1 = {
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.chip = {
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.label = "ramips-gpio1",
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.direction_input = ramips_gpio_direction_input,
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.direction_output = ramips_gpio_direction_output,
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.get = ramips_gpio_get,
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.set = ramips_gpio_set,
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.base = 32,
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.ngpio = RALINK_SOC_GPIO1_COUNT,
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},
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.regs = {
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[RAMIPS_GPIO_REG_INT] = GPIO1_REG_INT,
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[RAMIPS_GPIO_REG_EDGE] = GPIO1_REG_EDGE,
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[RAMIPS_GPIO_REG_RENA] = GPIO1_REG_RENA,
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[RAMIPS_GPIO_REG_FENA] = GPIO1_REG_FENA,
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[RAMIPS_GPIO_REG_DATA] = GPIO1_REG_DATA,
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[RAMIPS_GPIO_REG_DIR] = GPIO1_REG_DIR,
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[RAMIPS_GPIO_REG_POL] = GPIO1_REG_POL,
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[RAMIPS_GPIO_REG_SET] = GPIO1_REG_SET,
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[RAMIPS_GPIO_REG_RESET] = GPIO1_REG_RESET,
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[RAMIPS_GPIO_REG_TOGGLE] = GPIO1_REG_TOGGLE,
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},
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};
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static struct ramips_gpio_chip ramips_gpio_chip2 = {
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.chip = {
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.label = "ramips-gpio2",
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.direction_input = ramips_gpio_direction_input,
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.direction_output = ramips_gpio_direction_output,
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.get = ramips_gpio_get,
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.set = ramips_gpio_set,
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.base = 64,
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.ngpio = RALINK_SOC_GPIO2_COUNT,
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},
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.regs = {
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[RAMIPS_GPIO_REG_INT] = GPIO2_REG_INT,
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[RAMIPS_GPIO_REG_EDGE] = GPIO2_REG_EDGE,
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[RAMIPS_GPIO_REG_RENA] = GPIO2_REG_RENA,
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[RAMIPS_GPIO_REG_FENA] = GPIO2_REG_FENA,
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[RAMIPS_GPIO_REG_DATA] = GPIO2_REG_DATA,
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[RAMIPS_GPIO_REG_DIR] = GPIO2_REG_DIR,
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[RAMIPS_GPIO_REG_POL] = GPIO2_REG_POL,
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[RAMIPS_GPIO_REG_SET] = GPIO2_REG_SET,
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[RAMIPS_GPIO_REG_RESET] = GPIO2_REG_RESET,
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[RAMIPS_GPIO_REG_TOGGLE] = GPIO2_REG_TOGGLE,
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},
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};
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static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg)
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{
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spin_lock_init(&rg->lock);
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/* set polarity to low for all lines */
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ramips_gpio_wr(rg, RAMIPS_GPIO_REG_POL, 0);
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gpiochip_add(&rg->chip);
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}
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__init int ramips_gpio_init(void)
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{
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ramips_gpio_base = ioremap_nocache(RALINK_SOC_GPIO_BASE, PAGE_SIZE);
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ramips_gpio_chip_add(&ramips_gpio_chip0);
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ramips_gpio_chip_add(&ramips_gpio_chip1);
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ramips_gpio_chip_add(&ramips_gpio_chip2);
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return 0;
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}
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