mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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5ccc04ff5c
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19518 3c298f89-4303-0410-b956-a3cf2f4a3e73
179 lines
4.4 KiB
C
179 lines
4.4 KiB
C
/*
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* Copyright (C) 2008 Stanley Pinchak <stanley_dot_pinchak_at_gmail_dot_com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __AR7_TITAN_H__
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#define __AR7_TITAN_H__
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#ifndef __AR7_GPIO_H__
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#include <asm/ar7/gpio.h>
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#endif
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typedef enum TITAN_GPIO_PIN_MODE_tag
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{
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FUNCTIONAL_PIN = 0,
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GPIO_PIN = 1
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} TITAN_GPIO_PIN_MODE_T;
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typedef enum TITAN_GPIO_PIN_DIRECTION_tag
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{
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GPIO_OUTPUT_PIN = 0,
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GPIO_INPUT_PIN = 1
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} TITAN_GPIO_PIN_DIRECTION_T;
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/**********************************************************************
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* GPIO Control
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**********************************************************************/
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typedef struct
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{
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int pinSelReg;
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int shift;
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int func;
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} GPIO_CFG;
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static GPIO_CFG gptable[]= {
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/* PIN_SEL_REG, START_BIT, GPIO_CFG_MUX_VALUE */
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{4,24,1},
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{4,26,1},
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{4,28,1},
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{4,30,1},
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{5,6,1},
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{5,8,1},
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{5,10,1},
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{5,12,1},
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{7,14,3},
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{7,16,3},
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{7,18,3},
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{7,20,3},
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{7,22,3},
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{7,26,3},
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{7,28,3},
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{7,30,3},
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{8,0,3},
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{8,2,3},
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{8,4,3},
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{8,10,3},
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{8,14,3},
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{8,16,3},
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{8,18,3},
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{8,20,3},
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{9,8,3},
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{9,10,3},
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{9,12,3},
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{9,14,3},
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{9,18,3},
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{9,20,3},
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{9,24,3},
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{9,26,3},
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{9,28,3},
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{9,30,3},
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{10,0,3},
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{10,2,3},
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{10,8,3},
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{10,10,3},
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{10,12,3},
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{10,14,3},
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{13,12,3},
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{13,14,3},
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{13,16,3},
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{13,18,3},
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{13,24,3},
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{13,26,3},
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{13,28,3},
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{13,30,3},
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{14,2,3},
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{14,6,3},
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{14,8,3},
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{14,12,3}
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};
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typedef struct
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{
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volatile unsigned int reg[21];
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}
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PIN_SEL_REG_ARRAY_T;
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typedef struct
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{
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unsigned int data_in [2];
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unsigned int data_out[2];
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unsigned int dir[2];
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unsigned int enable[2];
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} TITAN_GPIO_CONTROL_T;
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#define AVALANCHE_PIN_SEL_BASE 0xA861160C /*replace with KSEG1ADDR()*/
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static inline int titan_gpio_ctrl(unsigned int gpio_pin, TITAN_GPIO_PIN_MODE_T pin_mode,
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TITAN_GPIO_PIN_DIRECTION_T pin_direction)
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{
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int reg_index = 0;
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int mux_status;
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GPIO_CFG gpio_cfg;
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volatile PIN_SEL_REG_ARRAY_T *pin_sel_array = (PIN_SEL_REG_ARRAY_T*) AVALANCHE_PIN_SEL_BASE;
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volatile TITAN_GPIO_CONTROL_T *gpio_cntl = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
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if (gpio_pin > 51 )
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return(-1);
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gpio_cfg = gptable[gpio_pin];
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mux_status = (pin_sel_array->reg[gpio_cfg.pinSelReg - 1] >> gpio_cfg.shift) & 0x3;
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if(!((mux_status == 0 /* tri-stated */ ) || (mux_status == gpio_cfg.func /*GPIO functionality*/)))
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{
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return(-1); /* Pin have been configured for non GPIO funcs. */
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}
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/* Set the pin to be used as GPIO. */
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pin_sel_array->reg[gpio_cfg.pinSelReg - 1] |= ((gpio_cfg.func & 0x3) << gpio_cfg.shift);
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/* Check whether gpio refers to the first GPIO reg or second. */
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if(gpio_pin > 31)
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{
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reg_index = 1;
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gpio_pin -= 32;
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}
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if(pin_mode)
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gpio_cntl->enable[reg_index] |= (1 << gpio_pin); /* Enable */
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else
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gpio_cntl->enable[reg_index] &= ~(1 << gpio_pin);
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if(pin_direction)
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gpio_cntl->dir[reg_index] |= (1 << gpio_pin); /* Input */
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else
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gpio_cntl->dir[reg_index] &= ~(1 << gpio_pin);
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return(0);
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}/* end of function titan_gpio_ctrl */
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static inline int titan_sysGpioInValue(unsigned int *in_val, unsigned int reg_index)
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{
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volatile TITAN_GPIO_CONTROL_T *gpio_cntl = (TITAN_GPIO_CONTROL_T*) KSEG1ADDR(AR7_REGS_GPIO + TITAN_GPIO_INPUT_0);
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if(reg_index > 1)
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return (-1);
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*in_val = gpio_cntl->data_in[reg_index];
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return (0);
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}
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#endif
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