1
0
mirror of git://projects.qi-hardware.com/openwrt-xburst.git synced 2024-09-18 19:40:15 +03:00
openwrt-xburst/target/linux/ar71xx/files/arch/mips/include/asm/mach-ath79/ag71xx_platform.h
nbd dfea949949 ar71xx: fix MII clock settings for various chips, improves ethernet stability on AR934x
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31925 3c298f89-4303-0410-b956-a3cf2f4a3e73
2012-05-27 21:02:41 +00:00

59 lines
1.2 KiB
C

/*
* Atheros AR71xx SoC specific platform data definitions
*
* Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __ASM_MACH_ATH79_PLATFORM_H
#define __ASM_MACH_ATH79_PLATFORM_H
#include <linux/if_ether.h>
#include <linux/skbuff.h>
#include <linux/phy.h>
#include <linux/spi/spi.h>
struct ag71xx_switch_platform_data {
u8 phy4_mii_en:1;
u8 phy_poll_mask;
};
struct ag71xx_platform_data {
phy_interface_t phy_if_mode;
u32 phy_mask;
int speed;
int duplex;
u32 reset_bit;
u8 mac_addr[ETH_ALEN];
struct device *mii_bus_dev;
u8 has_gbit:1;
u8 is_ar91xx:1;
u8 is_ar7240:1;
u8 is_ar724x:1;
u8 has_ar8216:1;
struct ag71xx_switch_platform_data *switch_data;
void (*ddr_flush)(void);
void (*set_speed)(int speed);
u32 fifo_cfg1;
u32 fifo_cfg2;
u32 fifo_cfg3;
};
struct ag71xx_mdio_platform_data {
u32 phy_mask;
u8 builtin_switch:1;
u8 is_ar7240:1;
u8 is_ar9330:1;
u8 is_ar934x:1;
};
#endif /* __ASM_MACH_ATH79_PLATFORM_H */