mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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c4105c81c0
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7284 3c298f89-4303-0410-b956-a3cf2f4a3e73
168 lines
5.2 KiB
C
168 lines
5.2 KiB
C
/**************************************************************************
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*
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* BRIEF MODULE DESCRIPTION
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* GPIO register definition
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*
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* Copyright 2004 IDT Inc. (rischelp@idt.com)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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**************************************************************************
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* May 2004 rkt, neb.
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*
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* Initial Release
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*
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*
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*
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**************************************************************************
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*/
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#ifndef __IDT_GPIO_H__
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#define __IDT_GPIO_H__
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enum
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{
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GPIO0_PhysicalAddress = 0x18050000,
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GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
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GPIO0_VirtualAddress = 0xb8050000,
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GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
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} ;
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typedef struct
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{
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u32 gpiofunc; /* GPIO Function Register
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* gpiofunc[x]==0 bit = gpio
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* func[x]==1 bit = altfunc
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*/
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u32 gpiocfg; /* GPIO Configuration Register
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* gpiocfg[x]==0 bit = input
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* gpiocfg[x]==1 bit = output
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*/
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u32 gpiod; /* GPIO Data Register
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* gpiod[x] read/write gpio pinX status
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*/
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u32 gpioilevel; /* GPIO Interrupt Status Register
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* interrupt level (see gpioistat)
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*/
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u32 gpioistat; /* Gpio Interrupt Status Register
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* istat[x] = (gpiod[x] == level[x])
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* cleared in ISR (STICKY bits)
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*/
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u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
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} volatile * GPIO_t ;
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typedef enum
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{
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GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
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GPIO_alt_v = 1, // gpiofunc use pin as alt.
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GPIO_input_v = 0, // gpiocfg use pin as input.
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GPIO_output_v = 1, // gpiocfg use pin as output.
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GPIO_pin0_b = 0,
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GPIO_pin0_m = 0x00000001,
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GPIO_pin1_b = 1,
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GPIO_pin1_m = 0x00000002,
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GPIO_pin2_b = 2,
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GPIO_pin2_m = 0x00000004,
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GPIO_pin3_b = 3,
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GPIO_pin3_m = 0x00000008,
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GPIO_pin4_b = 4,
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GPIO_pin4_m = 0x00000010,
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GPIO_pin5_b = 5,
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GPIO_pin5_m = 0x00000020,
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GPIO_pin6_b = 6,
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GPIO_pin6_m = 0x00000040,
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GPIO_pin7_b = 7,
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GPIO_pin7_m = 0x00000080,
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GPIO_pin8_b = 8,
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GPIO_pin8_m = 0x00000100,
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GPIO_pin9_b = 9,
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GPIO_pin9_m = 0x00000200,
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GPIO_pin10_b = 10,
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GPIO_pin10_m = 0x00000400,
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GPIO_pin11_b = 11,
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GPIO_pin11_m = 0x00000800,
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GPIO_pin12_b = 12,
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GPIO_pin12_m = 0x00001000,
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GPIO_pin13_b = 13,
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GPIO_pin13_m = 0x00002000,
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// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
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GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
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GPIO_u0sout_m = GPIO_pin0_m,
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GPIO_u0sout_cfg_v = GPIO_output_v,
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GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
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GPIO_u0sinp_m = GPIO_pin1_m,
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GPIO_u0sinp_cfg_v = GPIO_input_v,
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GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
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GPIO_u0rtsn_m = GPIO_pin2_m,
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GPIO_u0rtsn_cfg_v = GPIO_output_v,
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GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
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GPIO_u0ctsn_m = GPIO_pin3_m,
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GPIO_u0ctsn_cfg_v = GPIO_input_v,
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GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
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GPIO_maddr22_m = GPIO_pin4_m,
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GPIO_maddr22_cfg_v = GPIO_output_v,
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GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
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GPIO_maddr23_m = GPIO_pin5_m,
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GPIO_maddr23_cfg_v = GPIO_output_v,
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GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
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GPIO_maddr24_m = GPIO_pin6_m,
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GPIO_maddr24_cfg_v = GPIO_output_v,
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GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
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GPIO_maddr25_m = GPIO_pin7_m,
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GPIO_maddr25_cfg_v = GPIO_output_v,
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GPIO_cpudmadebug_b = GPIO_pin8_b, // CPU or DMA debug pin
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GPIO_cpudmadebug_m = GPIO_pin8_m,
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GPIO_cpudmadebug_cfg_v = GPIO_output_v,
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GPIO_pcireq4_b = GPIO_pin9_b, // PCI Request 4
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GPIO_pcireq4_m = GPIO_pin9_m,
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GPIO_pcireq4_cfg_v = GPIO_input_v,
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GPIO_pcigrant4_b = GPIO_pin10_b, // PCI Grant 4
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GPIO_pcigrant4_m = GPIO_pin10_m,
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GPIO_pcigrant4_cfg_v = GPIO_output_v,
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GPIO_pcireq5_b = GPIO_pin11_b, // PCI Request 5
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GPIO_pcireq5_m = GPIO_pin11_m,
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GPIO_pcireq5_cfg_v = GPIO_input_v,
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GPIO_pcigrant5_b = GPIO_pin12_b, // PCI Grant 5
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GPIO_pcigrant5_m = GPIO_pin12_m,
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GPIO_pcigrant5_cfg_v = GPIO_output_v,
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GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
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GPIO_pcimuintn_m = GPIO_pin13_m,
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GPIO_pcimuintn_cfg_v = GPIO_output_v,
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} GPIO_DEFS_t;
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#endif // __IDT_GPIO_H__
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