mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-14 17:44:38 +02:00
18a076fccd
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@24526 3c298f89-4303-0410-b956-a3cf2f4a3e73
246 lines
5.8 KiB
Diff
246 lines
5.8 KiB
Diff
--- a/drivers/mtd/maps/Kconfig
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+++ b/drivers/mtd/maps/Kconfig
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@@ -251,6 +251,12 @@
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help
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Support for flash chips on NETtel/SecureEdge/SnapGear boards.
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+config MTD_LANTIQ
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+ bool "Lantiq SoC NOR support"
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+ depends on LANTIQ && MTD_PARTITIONS
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+ help
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+ Support for NOR flsh chips on Lantiq SoC
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+
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config MTD_DILNETPC
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tristate "CFI Flash device mapped on DIL/Net PC"
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depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN
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--- a/drivers/mtd/maps/Makefile
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+++ b/drivers/mtd/maps/Makefile
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@@ -59,3 +59,4 @@
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obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o
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obj-$(CONFIG_MTD_VMU) += vmu-flash.o
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obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o
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+obj-$(CONFIG_MTD_LANTIQ) += lantiq.o
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--- /dev/null
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+++ b/drivers/mtd/maps/lantiq.c
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@@ -0,0 +1,169 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE
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+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/types.h>
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+#include <linux/kernel.h>
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+#include <linux/io.h>
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+#include <linux/init.h>
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/map.h>
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+#include <linux/mtd/partitions.h>
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+#include <linux/mtd/cfi.h>
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+#include <linux/magic.h>
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+#include <linux/platform_device.h>
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+#include <linux/mtd/physmap.h>
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+
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+#include <lantiq.h>
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+#include <lantiq_platform.h>
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+
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+static map_word
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+lq_read16(struct map_info *map, unsigned long adr)
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+{
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+ unsigned long flags;
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+ map_word temp;
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+ spin_lock_irqsave(&ebu_lock, flags);
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+ adr ^= 2;
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+ temp.x[0] = *((__u16 *)(map->virt + adr));
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+ spin_unlock_irqrestore(&ebu_lock, flags);
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+ return temp;
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+}
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+
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+static void
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+lq_write16(struct map_info *map, map_word d, unsigned long adr)
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+{
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+ unsigned long flags;
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+ spin_lock_irqsave(&ebu_lock, flags);
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+ adr ^= 2;
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+ *((__u16 *)(map->virt + adr)) = d.x[0];
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+ spin_unlock_irqrestore(&ebu_lock, flags);
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+}
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+
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+void
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+lq_copy_from(struct map_info *map, void *to,
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+ unsigned long from, ssize_t len)
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+{
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+ unsigned char *p;
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+ unsigned char *to_8;
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+ unsigned long flags;
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+ spin_lock_irqsave(&ebu_lock, flags);
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+ from = (unsigned long)(from + map->virt);
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+ p = (unsigned char *) from;
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+ to_8 = (unsigned char *) to;
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+ while (len--)
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+ *to_8++ = *p++;
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+ spin_unlock_irqrestore(&ebu_lock, flags);
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+}
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+
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+void
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+lq_copy_to(struct map_info *map, unsigned long to,
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+ const void *from, ssize_t len)
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+{
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+ unsigned char *p = (unsigned char *)from;
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+ unsigned char *to_8;
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+ unsigned long flags;
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+ spin_lock_irqsave(&ebu_lock, flags);
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+ to += (unsigned long) map->virt;
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+ to_8 = (unsigned char *)to;
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+ while (len--)
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+ *p++ = *to_8++;
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+ spin_unlock_irqrestore(&ebu_lock, flags);
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+}
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+
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+static const char *part_probe_types[] = { "cmdlinepart", NULL };
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+
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+static struct map_info lq_map = {
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+ .name = "lq_nor",
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+ .bankwidth = 2,
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+ .read = lq_read16,
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+ .write = lq_write16,
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+ .copy_from = lq_copy_from,
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+ .copy_to = lq_copy_to,
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+};
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+
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+static int
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+lq_mtd_probe(struct platform_device *pdev)
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+{
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+ struct physmap_flash_data *lq_mtd_data =
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+ (struct physmap_flash_data*) dev_get_platdata(&pdev->dev);
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+ struct mtd_info *lq_mtd = NULL;
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+ struct mtd_partition *parts = NULL;
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+ struct resource *res = 0;
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+ int nr_parts = 0;
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+
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+#ifdef CONFIG_SOC_LANTIQ_XWAY
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+ lq_w32(lq_r32(LQ_EBU_BUSCON0) & ~EBU_WRDIS, LQ_EBU_BUSCON0);
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+#endif
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ if(!res)
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+ {
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+ dev_err(&pdev->dev, "failed to get memory resource");
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+ return -ENOENT;
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+ }
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+ res = request_mem_region(res->start, resource_size(res),
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+ dev_name(&pdev->dev));
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+ if(!res)
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+ {
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+ dev_err(&pdev->dev, "failed to request mem resource");
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+ return -EBUSY;
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+ }
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+
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+ lq_map.phys = res->start;
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+ lq_map.size = resource_size(res);
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+ lq_map.virt = ioremap_nocache(lq_map.phys, lq_map.size);
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+
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+ if (!lq_map.virt ) {
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+ dev_err(&pdev->dev, "failed to ioremap!\n");
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+ return -EIO;
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+ }
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+
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+ lq_mtd = (struct mtd_info *) do_map_probe("cfi_probe", &lq_map);
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+ if (!lq_mtd) {
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+ iounmap(lq_map.virt);
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+ dev_err(&pdev->dev, "probing failed\n");
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+ return -ENXIO;
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+ }
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+
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+ lq_mtd->owner = THIS_MODULE;
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+
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+ nr_parts = parse_mtd_partitions(lq_mtd, part_probe_types, &parts, 0);
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+ if (nr_parts > 0) {
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+ dev_info(&pdev->dev, "using %d partitions from cmdline", nr_parts);
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+ } else {
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+ nr_parts = lq_mtd_data->nr_parts;
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+ parts = lq_mtd_data->parts;
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+ }
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+
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+ add_mtd_partitions(lq_mtd, parts, nr_parts);
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+ return 0;
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+}
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+
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+static struct platform_driver lq_mtd_driver = {
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+ .probe = lq_mtd_probe,
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+ .driver = {
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+ .name = "lq_nor",
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+ .owner = THIS_MODULE,
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+ },
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+};
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+
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+int __init
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+init_lq_mtd(void)
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+{
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+ int ret = platform_driver_register(&lq_mtd_driver);
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+ if (ret)
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+ printk(KERN_INFO "lq_nor: error registering platfom driver");
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+ return ret;
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+}
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+
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+module_init(init_lq_mtd);
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+
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+MODULE_LICENSE("GPL");
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+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
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+MODULE_DESCRIPTION("Lantiq SoC NOR");
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--- a/drivers/mtd/chips/cfi_cmdset_0001.c
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+++ b/drivers/mtd/chips/cfi_cmdset_0001.c
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@@ -41,7 +41,11 @@
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/* #define CMDSET0001_DISABLE_WRITE_SUSPEND */
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// debugging, turns off buffer write mode if set to 1
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-#define FORCE_WORD_WRITE 0
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+#ifdef CONFIG_LANTIQ
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+# define FORCE_WORD_WRITE 1
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+#else
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+# define FORCE_WORD_WRITE 0
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+#endif
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/* Intel chips */
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#define I82802AB 0x00ad
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@@ -1491,6 +1495,9 @@
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int ret=0;
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adr += chip->start;
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+#ifdef CONFIG_LANTIQ
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+ adr ^= 2;
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+#endif
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switch (mode) {
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case FL_WRITING:
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--- a/drivers/mtd/chips/cfi_cmdset_0002.c
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+++ b/drivers/mtd/chips/cfi_cmdset_0002.c
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@@ -40,7 +40,11 @@
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#include <linux/mtd/xip.h>
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#define AMD_BOOTLOC_BUG
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-#define FORCE_WORD_WRITE 0
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+#ifdef CONFIG_LANTIQ
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+# define FORCE_WORD_WRITE 1
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+#else
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+# define FORCE_WORD_WRITE 0
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+#endif
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#define MAX_WORD_RETRIES 3
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@@ -1156,6 +1160,10 @@
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adr += chip->start;
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+#ifdef CONFIG_LANTIQ
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+ adr ^= 2;
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+#endif
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+
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mutex_lock(&chip->mutex);
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ret = get_chip(map, chip, adr, FL_WRITING);
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if (ret) {
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