mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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b887a6d197
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17439 3c298f89-4303-0410-b956-a3cf2f4a3e73
119 lines
2.6 KiB
C
119 lines
2.6 KiB
C
/*
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* Ralink RT305x SoC specific interrupt handling
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*
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ralink/rt305x.h>
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#include <asm/mach-ralink/rt305x_regs.h>
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static void rt305x_intc_irq_dispatch(void)
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{
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u32 pending;
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pending = rt305x_intc_rr(INTC_REG_STATUS0);
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if (pending & RT305X_INTC_INT_TIMER0)
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do_IRQ(RT305X_INTC_IRQ_TIMER0);
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else if (pending & RT305X_INTC_INT_TIMER1)
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do_IRQ(RT305X_INTC_IRQ_TIMER1);
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else if (pending & RT305X_INTC_INT_UART0)
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do_IRQ(RT305X_INTC_IRQ_UART0);
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else if (pending & RT305X_INTC_INT_UART1)
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do_IRQ(RT305X_INTC_IRQ_UART1);
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/* TODO: handle PIO interrupts as well */
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else
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spurious_interrupt();
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}
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static void rt305x_intc_irq_unmask(unsigned int irq)
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{
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irq -= RT305X_INTC_IRQ_BASE;
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rt305x_intc_wr((1 << irq), INTC_REG_ENABLE);
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}
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static void rt305x_intc_irq_mask(unsigned int irq)
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{
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irq -= RT305X_INTC_IRQ_BASE;
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rt305x_intc_wr((1 << irq), INTC_REG_DISABLE);
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}
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struct irq_chip rt305x_intc_irq_chip = {
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.name = "RT305X INTC",
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.unmask = rt305x_intc_irq_unmask,
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.mask = rt305x_intc_irq_mask,
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.mask_ack = rt305x_intc_irq_mask,
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};
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static struct irqaction rt305x_intc_irqaction = {
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.handler = no_action,
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.name = "cascade [RT305X INTC]",
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};
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static void __init rt305x_intc_irq_init(void)
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{
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int i;
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/* disable all interrupts */
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rt305x_intc_wr(~0, INTC_REG_DISABLE);
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/* route all INTC interrupts to MIPS HW0 interrupt */
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rt305x_intc_wr(0, INTC_REG_TYPE);
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for (i = RT305X_INTC_IRQ_BASE;
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i < RT305X_INTC_IRQ_BASE + RT305X_INTC_IRQ_COUNT; i++) {
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set_irq_chip_and_handler(i, &rt305x_intc_irq_chip,
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handle_level_irq);
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}
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setup_irq(RT305X_CPU_IRQ_INTC, &rt305x_intc_irqaction);
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/* enable interrupt masking */
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rt305x_intc_wr(RT305X_INTC_INT_GLOBAL, INTC_REG_ENABLE);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending;
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pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (pending & STATUSF_IP7)
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do_IRQ(RT305X_CPU_IRQ_COUNTER);
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else if (pending & STATUSF_IP5)
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do_IRQ(RT305X_CPU_IRQ_FE);
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else if (pending & STATUSF_IP6)
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do_IRQ(RT305X_CPU_IRQ_WNIC);
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else if (pending & STATUSF_IP2)
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rt305x_intc_irq_dispatch();
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else
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spurious_interrupt();
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}
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void __init arch_init_irq(void)
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{
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mips_cpu_irq_init();
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rt305x_intc_irq_init();
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}
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