mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-06 21:31:33 +02:00
546b5ed544
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11894 3c298f89-4303-0410-b956-a3cf2f4a3e73
437 lines
9.5 KiB
C
437 lines
9.5 KiB
C
/*
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* Atheros AR71xx built-in ethernet mac driver
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*
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* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Based on Atheros' AG7100 driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include "ag71xx.h"
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#define AG71XX_MII_RETRY 1000
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#define AG71XX_MII_DELAY 5
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static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
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{
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__raw_writel(value, ag->mii_ctrl);
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}
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static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
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{
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return __raw_readl(ag->mii_ctrl);
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}
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void ag71xx_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)
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{
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u32 t;
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t = ag71xx_mii_ctrl_rr(ag);
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t &= ~(0x3);
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t |= (mii_if & 0x3);
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ag71xx_mii_ctrl_wr(ag, t);
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}
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void ag71xx_mii_ctrl_set_speed(struct ag71xx *ag, unsigned int speed)
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{
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u32 t;
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t = ag71xx_mii_ctrl_rr(ag);
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t &= ~(0x3 << 4);
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t |= (speed & 0x3) << 4;
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ag71xx_mii_ctrl_wr(ag, t);
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}
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static int ag71xx_mii_read(struct ag71xx *ag, int addr, int reg)
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{
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int ret;
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int i;
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ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
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ag71xx_wr(ag, AG71XX_REG_MII_ADDR,
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((addr & 0xff) << MII_ADDR_S) | (reg & 0xff));
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ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ);
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i = AG71XX_MII_RETRY;
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while (ag71xx_rr(ag, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
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if (i-- == 0) {
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printk(KERN_ERR "%s: mii_read timed out\n",
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ag->dev->name);
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ret = 0xffff;
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goto out;
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}
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udelay(AG71XX_MII_DELAY);
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}
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ret = ag71xx_rr(ag, AG71XX_REG_MII_STATUS) & 0xffff;
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ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
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DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret);
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out:
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return ret;
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}
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static void ag71xx_mii_write(struct ag71xx *ag, int addr, int reg, u16 val)
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{
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int i;
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DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val);
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ag71xx_wr(ag, AG71XX_REG_MII_ADDR,
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((addr & 0xff) << MII_ADDR_S) | (reg & 0xff));
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ag71xx_wr(ag, AG71XX_REG_MII_CTRL, val);
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i = AG71XX_MII_RETRY;
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while (ag71xx_rr(ag, AG71XX_REG_MII_IND) & MII_IND_BUSY) {
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if (i-- == 0) {
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printk(KERN_ERR "%s: mii_write timed out\n",
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ag->dev->name);
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break;
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}
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udelay(AG71XX_MII_DELAY);
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}
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}
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int ag71xx_mii_peek(struct ag71xx *ag)
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{
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int cnt;
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int i;
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cnt = 0;
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for (i = 0; i < PHY_MAX_ADDR; i++) {
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u16 bmsr, id1, id2, bmcr, advert, lpa;
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bmsr = ag71xx_mii_read(ag, i, MII_BMSR);
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bmcr = ag71xx_mii_read(ag, i, MII_BMCR);
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id1 = ag71xx_mii_read(ag, i, MII_PHYSID1);
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id2 = ag71xx_mii_read(ag, i, MII_PHYSID2);
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advert = ag71xx_mii_read(ag, i, MII_ADVERTISE);
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lpa = ag71xx_mii_read(ag, i, MII_LPA);
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DBG("%s: phy%02d bmsr=%04x, bmcr=%04x, "
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"id=%04x.%04x, advertise=%04x, lpa=%04x\n",
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ag->dev->name, i,
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bmsr, bmcr, id1, id2, advert, lpa);
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if ((bmsr | bmcr | id1 | id2 | advert | lpa) != 0)
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cnt++;
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}
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return cnt;
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}
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#define PLL_SEC_CONFIG 0x18050004
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#define PLL_ETH0_INT_CLOCK 0x18050010
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#define PLL_ETH1_INT_CLOCK 0x18050014
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#define PLL_ETH_EXT_CLOCK 0x18050018
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#define ag7100_pll_shift(_ag) (((_ag)->pdev->id) ? 19 : 17)
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#define ag7100_pll_offset(_ag) (((_ag)->pdev->id) ? PLL_ETH1_INT_CLOCK \
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: PLL_ETH0_INT_CLOCK)
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static void ag71xx_set_pll(struct ag71xx *ag, u32 pll_val)
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{
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void __iomem *pll_reg = ioremap_nocache(ag7100_pll_offset(ag), 4);
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void __iomem *pll_cfg = ioremap_nocache(PLL_SEC_CONFIG, 4);
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u32 s;
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u32 t;
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s = ag7100_pll_shift(ag);
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t = __raw_readl(pll_cfg);
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t &= ~(3 << s);
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t |= (2 << s);
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__raw_writel(t, pll_cfg);
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udelay(100);
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__raw_writel(pll_val, pll_reg);
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t |= (3 << s);
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__raw_writel(t, pll_cfg);
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udelay(100);
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t &= ~(3 << s);
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__raw_writel(t, pll_cfg);
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udelay(100);
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DBG("%s: pll_reg %#x: %#x\n", ag->dev->name,
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(unsigned int)pll_reg, __raw_readl(pll_reg));
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iounmap(pll_cfg);
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iounmap(pll_reg);
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}
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static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
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{
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switch (ag->speed) {
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case SPEED_1000:
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return "1000";
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case SPEED_100:
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return "100";
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case SPEED_10:
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return "10";
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}
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return "?";
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}
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#if 1
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#define PLL_VAL_1000 0x00110000
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#define PLL_VAL_100 0x00001099
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#define PLL_VAL_10 0x00991099
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#else
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#define PLL_VAL_1000 0x01111000
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#define PLL_VAL_100 0x09991000
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#define PLL_VAL_10 0x09991999
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#endif
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void ag71xx_link_update(struct ag71xx *ag)
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{
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u32 cfg2;
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u32 ifctl;
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u32 pll;
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u32 fifo5;
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u32 mii_speed;
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if (!ag->link) {
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netif_carrier_off(ag->dev);
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printk(KERN_INFO "%s: link down\n", ag->dev->name);
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return;
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}
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cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
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cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
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cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
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ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
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ifctl &= ~(MAC_IFCTL_SPEED);
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fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
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fifo5 &= ~FIFO_CFG5_BYTE_PER_CLK;
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switch (ag->speed) {
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case SPEED_1000:
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mii_speed = MII_CTRL_SPEED_1000;
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cfg2 |= MAC_CFG2_IF_1000;
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pll = PLL_VAL_1000;
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fifo5 |= FIFO_CFG5_BYTE_PER_CLK;
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break;
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case SPEED_100:
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mii_speed = MII_CTRL_SPEED_100;
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cfg2 |= MAC_CFG2_IF_10_100;
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ifctl |= MAC_IFCTL_SPEED;
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pll = PLL_VAL_100;
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break;
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case SPEED_10:
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mii_speed = MII_CTRL_SPEED_10;
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cfg2 |= MAC_CFG2_IF_10_100;
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pll = PLL_VAL_10;
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break;
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default:
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BUG();
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return;
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}
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
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ag71xx_set_pll(ag, pll);
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ag71xx_mii_ctrl_set_speed(ag, mii_speed);
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ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
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ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
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netif_carrier_on(ag->dev);
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printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
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ag->dev->name,
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ag71xx_speed_str(ag),
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(DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
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DBG("%s: fifo1=%#x, fifo2=%#x, fifo3=%#x, fifo4=%#x, fifo5=%#x\n",
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ag->dev->name,
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2),
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
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DBG("%s: mac_cfg2=%#x, ifctl=%#x, mii_ctrl=%#x\n",
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ag->dev->name,
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ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
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ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
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ag71xx_mii_ctrl_rr(ag));
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}
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static void ag71xx_link_adjust(struct net_device *dev)
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{
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struct ag71xx *ag = netdev_priv(dev);
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struct phy_device *phydev = ag->phy_dev;
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unsigned long flags;
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int status_change = 0;
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spin_lock_irqsave(&ag->lock, flags);
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if (phydev->link) {
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if (ag->duplex != phydev->duplex
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|| ag->speed != phydev->speed) {
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status_change = 1;
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}
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}
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if (phydev->link != ag->link) {
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if (phydev->link)
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netif_schedule(dev);
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status_change = 1;
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}
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ag->link = phydev->link;
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ag->duplex = phydev->duplex;
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ag->speed = phydev->speed;
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if (status_change)
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ag71xx_link_update(ag);
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spin_unlock_irqrestore(&ag->lock, flags);
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}
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static int ag71xx_mdio_read(struct mii_bus *bus, int addr, int reg)
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{
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struct ag71xx *ag = bus->priv;
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return ag71xx_mii_read(ag, addr, reg);
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}
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static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val)
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{
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struct ag71xx *ag = bus->priv;
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ag71xx_mii_write(ag, addr, reg, val);
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return 0;
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}
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static int ag71xx_mdio_reset(struct mii_bus *bus)
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{
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/* TODO */
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return 0;
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}
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static int ag71xx_mdio_probe(struct ag71xx *ag)
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{
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struct net_device *dev = ag->dev;
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struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
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struct phy_device *phydev = NULL;
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int phy_count = 0;
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int phy_addr;
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for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
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if (!(pdata->phy_mask & (1 << phy_addr)))
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continue;
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if (ag->mii_bus.phy_map[phy_addr] == NULL)
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continue;
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DBG("%s: PHY found at %s, uid=%08x\n",
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dev->name,
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ag->mii_bus.phy_map[phy_addr]->dev.bus_id,
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ag->mii_bus.phy_map[phy_addr]->phy_id);
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if (phydev == NULL)
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phydev = ag->mii_bus.phy_map[phy_addr];
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phy_count++;
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}
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switch (phy_count) {
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case 0:
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printk(KERN_ERR "%s: no PHY found\n", dev->name);
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return -ENODEV;
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case 1:
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ag->phy_dev = phy_connect(dev, phydev->dev.bus_id,
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&ag71xx_link_adjust, 0, pdata->phy_if_mode);
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if (IS_ERR(ag->phy_dev)) {
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printk(KERN_ERR "%s: could not connect to PHY at %s\n",
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dev->name, phydev->dev.bus_id);
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return PTR_ERR(ag->phy_dev);
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}
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/* mask with MAC supported features */
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phydev->supported &= (SUPPORTED_10baseT_Half
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| SUPPORTED_10baseT_Full
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| SUPPORTED_100baseT_Half
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| SUPPORTED_100baseT_Full
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| SUPPORTED_Autoneg
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| SUPPORTED_MII
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| SUPPORTED_TP);
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phydev->advertising = phydev->supported;
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printk(KERN_DEBUG "%s: connected to PHY at %s "
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"[uid=%08x, driver=%s]\n",
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dev->name, phydev->dev.bus_id,
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phydev->phy_id, phydev->drv->name);
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ag->link = 0;
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ag->speed = 0;
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ag->duplex = -1;
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break;
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default:
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ag->phy_dev = NULL;
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printk(KERN_DEBUG "%s: connected to multiple PHYs (%d)\n",
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dev->name, phy_count);
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break;
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}
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return 0;
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}
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int ag71xx_mdio_init(struct ag71xx *ag, int id)
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{
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int err;
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int i;
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ag->mii_bus.name = "ag71xx_mii";
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ag->mii_bus.read = ag71xx_mdio_read;
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ag->mii_bus.write = ag71xx_mdio_write;
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ag->mii_bus.reset = ag71xx_mdio_reset;
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ag->mii_bus.id = id;
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ag->mii_bus.priv = ag;
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ag->mii_bus.dev = &ag->dev->dev;
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ag->mii_bus.irq = kmalloc(sizeof(*ag->mii_bus.irq) * PHY_MAX_ADDR,
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GFP_KERNEL);
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if (!ag->mii_bus.irq) {
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err = -ENOMEM;
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goto err_out;
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}
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for (i = 0; i < PHY_MAX_ADDR; i++)
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ag->mii_bus.irq[i] = PHY_POLL;
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err = mdiobus_register(&ag->mii_bus);
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if (err)
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goto err_free_irqs;
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err = ag71xx_mdio_probe(ag);
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if (err)
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goto err_unregister_bus;
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return 0;
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err_unregister_bus:
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mdiobus_unregister(&ag->mii_bus);
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err_free_irqs:
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kfree(ag->mii_bus.irq);
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err_out:
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return err;
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}
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void ag71xx_mdio_cleanup(struct ag71xx *ag)
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{
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mdiobus_unregister(&ag->mii_bus);
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kfree(ag->mii_bus.irq);
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}
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