mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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796a9d1091
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@15242 3c298f89-4303-0410-b956-a3cf2f4a3e73
86 lines
2.1 KiB
C
86 lines
2.1 KiB
C
/*
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* BCM47XX Sonics SiliconBackplane embedded ram core
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*
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* Copyright 2007, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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*/
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#ifndef _SBSOCRAM_H
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#define _SBSOCRAM_H
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#ifndef _LANGUAGE_ASSEMBLY
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/* cpp contortions to concatenate w/arg prescan */
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#ifndef PAD
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#define _PADLINE(line) pad ## line
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#define _XSTR(line) _PADLINE(line)
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#define PAD _XSTR(__LINE__)
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#endif /* PAD */
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/* Memcsocram core registers */
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typedef volatile struct sbsocramregs {
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uint32 coreinfo;
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uint32 bwalloc;
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uint32 PAD;
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uint32 biststat;
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uint32 bankidx;
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uint32 standbyctrl;
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uint32 PAD[116];
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uint32 pwrctl; /* corerev >= 2 */
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} sbsocramregs_t;
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#endif /* _LANGUAGE_ASSEMBLY */
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/* Register offsets */
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#define SR_COREINFO 0x00
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#define SR_BWALLOC 0x04
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#define SR_BISTSTAT 0x0c
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#define SR_BANKINDEX 0x10
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#define SR_BANKSTBYCTL 0x14
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#define SR_PWRCTL 0x1e8
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/* Coreinfo register */
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#define SRCI_PT_MASK 0x00030000
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#define SRCI_PT_SHIFT 16
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/* corerev >= 3 */
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#define SRCI_LSS_MASK 0x00f00000
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#define SRCI_LSS_SHIFT 20
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#define SRCI_LRS_MASK 0x0f000000
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#define SRCI_LRS_SHIFT 24
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/* In corerev 0, the memory size is 2 to the power of the
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* base plus 16 plus to the contents of the memsize field plus 1.
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*/
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#define SRCI_MS0_MASK 0xf
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#define SR_MS0_BASE 16
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/*
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* In corerev 1 the bank size is 2 ^ the bank size field plus 14,
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* the memory size is number of banks times bank size.
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* The same applies to rom size.
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*/
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#define SRCI_ROMNB_MASK 0xf000
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#define SRCI_ROMNB_SHIFT 12
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#define SRCI_ROMBSZ_MASK 0xf00
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#define SRCI_ROMBSZ_SHIFT 8
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#define SRCI_SRNB_MASK 0xf0
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#define SRCI_SRNB_SHIFT 4
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#define SRCI_SRBSZ_MASK 0xf
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#define SRCI_SRBSZ_SHIFT 0
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#define SR_BSZ_BASE 14
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/* Standby control register */
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#define SRSC_SBYOVR_MASK 0x80000000
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#define SRSC_SBYOVR_SHIFT 31
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#define SRSC_SBYOVRVAL_MASK 0x60000000
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#define SRSC_SBYOVRVAL_SHIFT 29
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#endif /* _SBSOCRAM_H */
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