mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-20 18:13:43 +02:00
c1f8025fcd
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@7181 3c298f89-4303-0410-b956-a3cf2f4a3e73
112 lines
3.6 KiB
C
112 lines
3.6 KiB
C
/*==============================================================================*/
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/* rbmipsnand.c */
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/* This module is derived from the 2.4 driver shipped by Microtik for their */
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/* Routerboard 1xx and 5xx series boards. It provides support for the built in */
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/* NAND flash on the Routerboard 1xx series boards for Linux 2.6.19+. */
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/* Licence: Original Microtik code seems not to have a licence. */
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/* Rewritten code all GPL V2. */
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/* Copyright(C) 2007 david.goodenough@linkchoose.co.uk (for rewriten code) */
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/*==============================================================================*/
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#include <linux/init.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/bootinfo.h>
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#define SMEM1_BASE 0x10000000 // from ADM5120 documentation
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#define SMEM1(x) (*((volatile unsigned char *) (KSEG1ADDR(SMEM1_BASE) + x)))
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#define NAND_RW_REG 0x0 //data register
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#define NAND_SET_CEn 0x1 //CE# low
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#define NAND_CLR_CEn 0x2 //CE# high
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#define NAND_CLR_CLE 0x3 //CLE low
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#define NAND_SET_CLE 0x4 //CLE high
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#define NAND_CLR_ALE 0x5 //ALE low
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#define NAND_SET_ALE 0x6 //ALE high
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#define NAND_SET_SPn 0x7 //SP# low (use spare area)
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#define NAND_CLR_SPn 0x8 //SP# high (do not use spare area)
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#define NAND_SET_WPn 0x9 //WP# low
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#define NAND_CLR_WPn 0xA //WP# high
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#define NAND_STS_REG 0xB //Status register
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#define MEM32(x) *((volatile unsigned *) (x))
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static void __iomem *p_nand;
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static int rb100_dev_ready(struct mtd_info *mtd) {
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return SMEM1(NAND_STS_REG) & 0x80;
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}
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static void rbmips_hwcontrol100(struct mtd_info *mtd, int cmd, unsigned int ctrl) {
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struct nand_chip *chip = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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SMEM1((( ctrl & NAND_CLE) ? NAND_SET_CLE : NAND_CLR_CLE)) = 0x01;
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SMEM1((( ctrl & NAND_ALE) ? NAND_SET_ALE : NAND_CLR_ALE)) = 0x01;
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SMEM1((( ctrl & NAND_NCE) ? NAND_SET_CEn : NAND_CLR_CEn)) = 0x01;
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}
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if( cmd != NAND_CMD_NONE)
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writeb( cmd, chip->IO_ADDR_W);
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}
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static struct mtd_partition partition_info[] = {
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{
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name: "RouterBoard NAND Boot",
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offset: 0,
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size: 4 * 1024 * 1024
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},
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{
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name: "RouterBoard NAND Main",
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offset: MTDPART_OFS_NXTBLK,
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size: MTDPART_SIZ_FULL
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}
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};
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static struct mtd_info rmtd;
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static struct nand_chip rnand;
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static unsigned init_ok = 0;
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unsigned get_rbnand_block_size(void) {
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return init_ok ? rmtd.writesize : 0;
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}
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EXPORT_SYMBOL(get_rbnand_block_size);
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int __init rbmips_init(void) {
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memset(&rmtd, 0, sizeof(rmtd));
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memset(&rnand, 0, sizeof(rnand));
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printk(KERN_INFO "RB1xx nand\n");
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MEM32(0xB2000064) = 0x100;
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MEM32(0xB2000008) = 0x1;
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SMEM1(NAND_SET_SPn) = 0x01;
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SMEM1(NAND_CLR_WPn) = 0x01;
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rnand.IO_ADDR_R = (unsigned char *)KSEG1ADDR(SMEM1_BASE);
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rnand.IO_ADDR_W = rnand.IO_ADDR_R;
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rnand.cmd_ctrl = rbmips_hwcontrol100;
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rnand.dev_ready = rb100_dev_ready;
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p_nand = (void __iomem *)ioremap(( unsigned long)SMEM1_BASE, 0x1000);
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if (!p_nand) {
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printk(KERN_WARNING "RB1xx nand Unable ioremap buffer\n");
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return -ENXIO;
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}
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rnand.ecc.mode = NAND_ECC_SOFT;
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rnand.chip_delay = 25;
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rnand.options |= NAND_NO_AUTOINCR;
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rmtd.priv = &rnand;
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if (nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1)
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&& nand_scan(&rmtd, 1) && nand_scan(&rmtd, 1)) {
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printk(KERN_INFO "RB1xxx nand device not found\n");
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iounmap ((void *)p_nand);
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return -ENXIO;
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}
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add_mtd_partitions(&rmtd, partition_info, 2);
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init_ok = 1;
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return 0;
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}
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module_init(rbmips_init);
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