mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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0a2b2965cd
* bump kernel to 2.6.35.8 * merge arcadyn mach files * fixes ar9 * adds hack for tapi drivers git-svn-id: svn://svn.openwrt.org/openwrt/trunk@23836 3c298f89-4303-0410-b956-a3cf2f4a3e73
552 lines
15 KiB
C
552 lines
15 KiB
C
/*
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* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Copyright (C) 2004 Infineon IFAP DC COM CPE
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* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/major.h>
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#include <linux/string.h>
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#include <linux/fcntl.h>
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#include <linux/ptrace.h>
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#include <linux/ioport.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/circ_buf.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/uaccess.h>
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#include <linux/bitops.h>
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#include <asm/system.h>
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#include <ifxmips.h>
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#include <ifxmips_irq.h>
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#define PORT_IFXMIPSASC 111
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#include <linux/serial_core.h>
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#define UART_DUMMY_UER_RX 1
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static void ifxmipsasc_tx_chars(struct uart_port *port);
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extern void prom_printf(const char *fmt, ...);
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static struct uart_port ifxmipsasc_port[2];
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static struct uart_driver ifxmipsasc_reg;
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extern unsigned int ifxmips_get_fpi_hz(void);
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static void ifxmipsasc_stop_tx(struct uart_port *port)
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{
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return;
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}
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static void ifxmipsasc_start_tx(struct uart_port *port)
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{
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unsigned long flags;
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local_irq_save(flags);
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ifxmipsasc_tx_chars(port);
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local_irq_restore(flags);
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return;
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}
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static void ifxmipsasc_stop_rx(struct uart_port *port)
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{
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ifxmips_w32(ASCWHBSTATE_CLRREN, port->membase + IFXMIPS_ASC_WHBSTATE);
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}
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static void ifxmipsasc_enable_ms(struct uart_port *port)
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{
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}
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#include <linux/version.h>
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static void ifxmipsasc_rx_chars(struct uart_port *port)
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{
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struct tty_struct *tty = port->state->port.tty;
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unsigned int ch = 0, rsr = 0, fifocnt;
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fifocnt = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
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while (fifocnt--) {
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u8 flag = TTY_NORMAL;
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ch = ifxmips_r32(port->membase + IFXMIPS_ASC_RBUF);
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rsr = (ifxmips_r32(port->membase + IFXMIPS_ASC_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
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tty_flip_buffer_push(tty);
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port->icount.rx++;
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/*
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* Note that the error handling code is
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* out of the main execution path
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*/
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if (rsr & ASCSTATE_ANY) {
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if (rsr & ASCSTATE_PE) {
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port->icount.parity++;
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE, port->membase + IFXMIPS_ASC_WHBSTATE);
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} else if (rsr & ASCSTATE_FE) {
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port->icount.frame++;
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRFE, port->membase + IFXMIPS_ASC_WHBSTATE);
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}
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if (rsr & ASCSTATE_ROE) {
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port->icount.overrun++;
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE);
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}
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rsr &= port->read_status_mask;
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if (rsr & ASCSTATE_PE)
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flag = TTY_PARITY;
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else if (rsr & ASCSTATE_FE)
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flag = TTY_FRAME;
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}
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if ((rsr & port->ignore_status_mask) == 0)
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tty_insert_flip_char(tty, ch, flag);
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if (rsr & ASCSTATE_ROE)
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/*
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* Overrun is special, since it's reported
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* immediately, and doesn't affect the current
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* character
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*/
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tty_insert_flip_char(tty, 0, TTY_OVERRUN);
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}
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if (ch != 0)
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tty_flip_buffer_push(tty);
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return;
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}
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static void ifxmipsasc_tx_chars(struct uart_port *port)
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{
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struct circ_buf *xmit = &port->state->xmit;
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if (uart_tx_stopped(port)) {
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ifxmipsasc_stop_tx(port);
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return;
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}
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while (((ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK)
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>> ASCFSTAT_TXFFLOFF) != TXFIFO_FULL) {
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if (port->x_char) {
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ifxmips_w32(port->x_char, port->membase + IFXMIPS_ASC_TBUF);
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port->icount.tx++;
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port->x_char = 0;
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continue;
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}
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if (uart_circ_empty(xmit))
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break;
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ifxmips_w32(port->state->xmit.buf[port->state->xmit.tail], port->membase + IFXMIPS_ASC_TBUF);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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}
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static irqreturn_t ifxmipsasc_tx_int(int irq, void *_port)
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{
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struct uart_port *port = (struct uart_port *)_port;
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ifxmips_w32(ASC_IRNCR_TIR, port->membase + IFXMIPS_ASC_IRNCR);
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ifxmipsasc_start_tx(port);
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ifxmips_mask_and_ack_irq(irq);
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return IRQ_HANDLED;
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}
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static irqreturn_t ifxmipsasc_er_int(int irq, void *_port)
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{
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struct uart_port *port = (struct uart_port *)_port;
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/* clear any pending interrupts */
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE |
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ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE);
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return IRQ_HANDLED;
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}
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static irqreturn_t ifxmipsasc_rx_int(int irq, void *_port)
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{
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struct uart_port *port = (struct uart_port *)_port;
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ifxmips_w32(ASC_IRNCR_RIR, port->membase + IFXMIPS_ASC_IRNCR);
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ifxmipsasc_rx_chars((struct uart_port *)port);
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ifxmips_mask_and_ack_irq(irq);
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return IRQ_HANDLED;
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}
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static unsigned int ifxmipsasc_tx_empty(struct uart_port *port)
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{
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int status;
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status = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
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return status ? 0 : TIOCSER_TEMT;
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}
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static unsigned int ifxmipsasc_get_mctrl(struct uart_port *port)
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{
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return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
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}
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static void ifxmipsasc_set_mctrl(struct uart_port *port, u_int mctrl)
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{
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}
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static void ifxmipsasc_break_ctl(struct uart_port *port, int break_state)
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{
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}
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static int ifxmipsasc_startup(struct uart_port *port)
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{
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int retval;
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port->uartclk = ifxmips_get_fpi_hz();
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~IFXMIPS_ASC_CLC_DISS, port->membase + IFXMIPS_ASC_CLC);
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ifxmips_w32(((ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~ASCCLC_RMCMASK)) | (1 << ASCCLC_RMCOFFSET), port->membase + IFXMIPS_ASC_CLC);
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ifxmips_w32(0, port->membase + IFXMIPS_ASC_PISEL);
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ifxmips_w32(((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
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ifxmips_w32(((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
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wmb();
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN, port->membase + IFXMIPS_ASC_CON);
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retval = request_irq(port->irq, ifxmipsasc_tx_int, IRQF_DISABLED, "asc_tx", port);
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if (retval) {
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printk(KERN_ERR "failed to request ifxmipsasc_tx_int\n");
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return retval;
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}
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retval = request_irq(port->irq + 2, ifxmipsasc_rx_int, IRQF_DISABLED, "asc_rx", port);
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if (retval) {
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printk(KERN_ERR "failed to request ifxmipsasc_rx_int\n");
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goto err1;
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}
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retval = request_irq(port->irq + 3, ifxmipsasc_er_int, IRQF_DISABLED, "asc_er", port);
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if (retval) {
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printk(KERN_ERR "failed to request ifxmipsasc_er_int\n");
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goto err2;
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}
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ifxmips_w32(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX, port->membase + IFXMIPS_ASC_IRNREN);
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return 0;
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err2:
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free_irq(port->irq + 2, port);
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err1:
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free_irq(port->irq, port);
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return retval;
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}
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static void ifxmipsasc_shutdown(struct uart_port *port)
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{
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free_irq(port->irq, port);
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free_irq(port->irq + 2, port);
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free_irq(port->irq + 3, port);
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ifxmips_w32(0, port->membase + IFXMIPS_ASC_CON);
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON);
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) & ~ASCRXFCON_RXFEN, port->membase + IFXMIPS_ASC_RXFCON);
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON);
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) & ~ASCTXFCON_TXFEN, port->membase + IFXMIPS_ASC_TXFCON);
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}
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static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
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{
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unsigned int cflag;
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unsigned int iflag;
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unsigned int quot;
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unsigned int baud;
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unsigned int con = 0;
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unsigned long flags;
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cflag = new->c_cflag;
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iflag = new->c_iflag;
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switch (cflag & CSIZE) {
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case CS7:
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con = ASCCON_M_7ASYNC;
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break;
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case CS5:
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case CS6:
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default:
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con = ASCCON_M_8ASYNC;
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break;
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}
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if (cflag & CSTOPB)
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con |= ASCCON_STP;
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if (cflag & PARENB) {
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if (!(cflag & PARODD))
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con &= ~ASCCON_ODD;
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else
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con |= ASCCON_ODD;
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}
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port->read_status_mask = ASCSTATE_ROE;
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if (iflag & INPCK)
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port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
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port->ignore_status_mask = 0;
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if (iflag & IGNPAR)
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port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
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if (iflag & IGNBRK) {
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/*
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* If we're ignoring parity and break indicators,
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* ignore overruns too (for real raw support).
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*/
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if (iflag & IGNPAR)
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port->ignore_status_mask |= ASCSTATE_ROE;
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}
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if ((cflag & CREAD) == 0)
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port->ignore_status_mask |= UART_DUMMY_UER_RX;
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/* set error signals - framing, parity and overrun, enable receiver */
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con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
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local_irq_save(flags);
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/* set up CON */
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | con, port->membase + IFXMIPS_ASC_CON);
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/* Set baud rate - take a divider of 2 into account */
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baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
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quot = uart_get_divisor(port, baud);
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quot = quot / 2 - 1;
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/* disable the baudrate generator */
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_R, port->membase + IFXMIPS_ASC_CON);
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/* make sure the fractional divider is off */
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_FDE, port->membase + IFXMIPS_ASC_CON);
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/* set up to use divisor of 2 */
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_BRS, port->membase + IFXMIPS_ASC_CON);
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/* now we can write the new baudrate into the register */
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ifxmips_w32(quot, port->membase + IFXMIPS_ASC_BG);
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/* turn the baudrate generator back on */
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ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_R, port->membase + IFXMIPS_ASC_CON);
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/* enable rx */
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ifxmips_w32(ASCWHBSTATE_SETREN, port->membase + IFXMIPS_ASC_WHBSTATE);
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local_irq_restore(flags);
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}
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static const char *ifxmipsasc_type(struct uart_port *port)
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{
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if (port->type == PORT_IFXMIPSASC) {
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if (port->membase == (void *)IFXMIPS_ASC_BASE_ADDR)
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return "asc0";
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else
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return "asc1";
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} else {
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return NULL;
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}
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}
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static void ifxmipsasc_release_port(struct uart_port *port)
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{
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}
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static int ifxmipsasc_request_port(struct uart_port *port)
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{
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return 0;
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}
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static void ifxmipsasc_config_port(struct uart_port *port, int flags)
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{
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if (flags & UART_CONFIG_TYPE) {
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port->type = PORT_IFXMIPSASC;
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ifxmipsasc_request_port(port);
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}
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}
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static int ifxmipsasc_verify_port(struct uart_port *port, struct serial_struct *ser)
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{
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int ret = 0;
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if (ser->type != PORT_UNKNOWN && ser->type != PORT_IFXMIPSASC)
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ret = -EINVAL;
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if (ser->irq < 0 || ser->irq >= NR_IRQS)
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ret = -EINVAL;
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if (ser->baud_base < 9600)
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ret = -EINVAL;
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return ret;
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}
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static struct uart_ops ifxmipsasc_pops = {
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.tx_empty = ifxmipsasc_tx_empty,
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.set_mctrl = ifxmipsasc_set_mctrl,
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.get_mctrl = ifxmipsasc_get_mctrl,
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.stop_tx = ifxmipsasc_stop_tx,
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.start_tx = ifxmipsasc_start_tx,
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.stop_rx = ifxmipsasc_stop_rx,
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.enable_ms = ifxmipsasc_enable_ms,
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.break_ctl = ifxmipsasc_break_ctl,
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.startup = ifxmipsasc_startup,
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.shutdown = ifxmipsasc_shutdown,
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.set_termios = ifxmipsasc_set_termios,
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.type = ifxmipsasc_type,
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.release_port = ifxmipsasc_release_port,
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.request_port = ifxmipsasc_request_port,
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.config_port = ifxmipsasc_config_port,
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.verify_port = ifxmipsasc_verify_port,
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};
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static struct uart_port ifxmipsasc_port[2] = {
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{
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.membase = (void *)IFXMIPS_ASC_BASE_ADDR,
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.mapbase = IFXMIPS_ASC_BASE_ADDR,
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.iotype = SERIAL_IO_MEM,
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.irq = IFXMIPSASC_TIR(0),
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.uartclk = 0,
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.fifosize = 16,
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.type = PORT_IFXMIPSASC,
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.ops = &ifxmipsasc_pops,
|
|
.flags = ASYNC_BOOT_AUTOCONF,
|
|
.line = 0
|
|
}, {
|
|
.membase = (void *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF),
|
|
.mapbase = IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF,
|
|
.iotype = SERIAL_IO_MEM,
|
|
.irq = IFXMIPSASC_TIR(1),
|
|
.uartclk = 0,
|
|
.fifosize = 16,
|
|
.type = PORT_IFXMIPSASC,
|
|
.ops = &ifxmipsasc_pops,
|
|
.flags = ASYNC_BOOT_AUTOCONF,
|
|
.line = 1
|
|
}
|
|
};
|
|
|
|
static void ifxmipsasc_console_write(struct console *co, const char *s, u_int count)
|
|
{
|
|
int port = co->index;
|
|
int i, fifocnt;
|
|
unsigned long flags;
|
|
local_irq_save(flags);
|
|
for (i = 0; i < count; i++) {
|
|
do {
|
|
fifocnt = (ifxmips_r32((u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
|
|
>> ASCFSTAT_TXFFLOFF;
|
|
} while (fifocnt == TXFIFO_FULL);
|
|
|
|
if (s[i] == '\0')
|
|
break;
|
|
|
|
if (s[i] == '\n') {
|
|
ifxmips_w32('\r', (u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
|
|
do {
|
|
fifocnt = (ifxmips_r32((u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK)
|
|
>> ASCFSTAT_TXFFLOFF;
|
|
} while (fifocnt == TXFIFO_FULL);
|
|
}
|
|
ifxmips_w32(s[i], (u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF));
|
|
}
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
static int __init ifxmipsasc_console_setup(struct console *co, char *options)
|
|
{
|
|
int port = co->index;
|
|
int baud = 115200;
|
|
int bits = 8;
|
|
int parity = 'n';
|
|
int flow = 'n';
|
|
ifxmipsasc_port[port].uartclk = ifxmips_get_fpi_hz();
|
|
ifxmipsasc_port[port].type = PORT_IFXMIPSASC;
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
return uart_set_options(&ifxmipsasc_port[port], co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static struct console ifxmipsasc_console[2] =
|
|
{
|
|
{
|
|
.name = "ttyS",
|
|
.write = ifxmipsasc_console_write,
|
|
.device = uart_console_device,
|
|
.setup = ifxmipsasc_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = 0,
|
|
.data = &ifxmipsasc_reg,
|
|
}, {
|
|
.name = "ttyS",
|
|
.write = ifxmipsasc_console_write,
|
|
.device = uart_console_device,
|
|
.setup = ifxmipsasc_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = 1,
|
|
.data = &ifxmipsasc_reg,
|
|
}
|
|
};
|
|
|
|
static int __init ifxmipsasc_console_init(void)
|
|
{
|
|
register_console(&ifxmipsasc_console[0]);
|
|
register_console(&ifxmipsasc_console[1]);
|
|
return 0;
|
|
}
|
|
console_initcall(ifxmipsasc_console_init);
|
|
|
|
static struct uart_driver ifxmipsasc_reg = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = "serial",
|
|
.dev_name = "ttyS",
|
|
.major = TTY_MAJOR,
|
|
.minor = 64,
|
|
.nr = 2,
|
|
.cons = &ifxmipsasc_console[1],
|
|
};
|
|
|
|
int __init ifxmipsasc_init(void)
|
|
{
|
|
int ret;
|
|
uart_register_driver(&ifxmipsasc_reg);
|
|
ret = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[0]);
|
|
ret = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[1]);
|
|
return 0;
|
|
}
|
|
|
|
void __exit ifxmipsasc_exit(void)
|
|
{
|
|
uart_unregister_driver(&ifxmipsasc_reg);
|
|
}
|
|
|
|
module_init(ifxmipsasc_init);
|
|
module_exit(ifxmipsasc_exit);
|
|
|
|
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
|
|
MODULE_DESCRIPTION("MIPS IFXMips serial port driver");
|
|
MODULE_LICENSE("GPL");
|