mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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4f531230a3
openwrt. this gives us the ability to better support different hardware models, without changing any external tar-balls. only et.o and wl.o is missing and is fetched from my webserver. git-svn-id: svn://svn.openwrt.org/openwrt/trunk/openwrt@379 3c298f89-4303-0410-b956-a3cf2f4a3e73
230 lines
7.3 KiB
C
230 lines
7.3 KiB
C
/*
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* Hardware-specific definitions for
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* Broadcom BCM47XX 10/100 Mbps Ethernet cores.
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*
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* Copyright 2004, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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* $Id$
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*/
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#ifndef _bcmenet_47xx_h_
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#define _bcmenet_47xx_h_
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#include <bcmdevs.h>
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#include <hnddma.h>
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#define BCMENET_NFILTERS 64 /* # ethernet address filter entries */
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#define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */
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#define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */
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#define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */
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/* power management event wakeup pattern constants */
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#define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */
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#define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */
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#define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */
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#define BCMENET_PMMBASE 0x600 /* wakeup mask base address */
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#define BCMENET_PMMSIZE 0x10 /* 128bits each mask */
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/* cpp contortions to concatenate w/arg prescan */
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#ifndef PAD
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#define _PADLINE(line) pad ## line
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#define _XSTR(line) _PADLINE(line)
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#define PAD _XSTR(__LINE__)
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#endif /* PAD */
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/* sometimes you just need the enet mib definitions */
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#include <bcmenetmib.h>
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/*
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* Host Interface Registers
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*/
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typedef volatile struct _bcmenettregs {
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/* Device and Power Control */
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uint32 devcontrol;
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uint32 PAD[2];
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uint32 biststatus;
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uint32 wakeuplength;
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uint32 PAD[3];
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/* Interrupt Control */
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uint32 intstatus;
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uint32 intmask;
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uint32 gptimer;
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uint32 PAD[23];
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/* Ethernet MAC Address Filtering Control */
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uint32 PAD[2];
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uint32 enetftaddr;
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uint32 enetftdata;
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uint32 PAD[2];
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/* Ethernet MAC Control */
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uint32 emactxmaxburstlen;
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uint32 emacrxmaxburstlen;
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uint32 emaccontrol;
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uint32 emacflowcontrol;
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uint32 PAD[20];
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/* DMA Lazy Interrupt Control */
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uint32 intrecvlazy;
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uint32 PAD[63];
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/* DMA engine */
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dmaregs_t dmaregs;
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dmafifo_t dmafifo;
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uint32 PAD[116];
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/* EMAC Registers */
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uint32 rxconfig;
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uint32 rxmaxlength;
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uint32 txmaxlength;
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uint32 PAD;
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uint32 mdiocontrol;
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uint32 mdiodata;
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uint32 emacintmask;
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uint32 emacintstatus;
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uint32 camdatalo;
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uint32 camdatahi;
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uint32 camcontrol;
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uint32 enetcontrol;
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uint32 txcontrol;
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uint32 txwatermark;
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uint32 mibcontrol;
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uint32 PAD[49];
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/* EMAC MIB counters */
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bcmenetmib_t mib;
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uint32 PAD[585];
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/* Sonics SiliconBackplane config registers */
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sbconfig_t sbconfig;
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} bcmenetregs_t;
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/* device control */
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#define DC_PM ((uint32)1 << 7) /* pattern filtering enable */
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#define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */
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#define DC_ER ((uint32)1 << 15) /* ephy reset */
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#define DC_MP ((uint32)1 << 16) /* mii phy mode enable */
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#define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */
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#define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */
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#define DC_PA_SHIFT 18
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/* wakeup length */
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#define WL_P0_MASK 0x7f /* pattern 0 */
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#define WL_D0 ((uint32)1 << 7)
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#define WL_P1_MASK 0x7f00 /* pattern 1 */
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#define WL_P1_SHIFT 8
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#define WL_D1 ((uint32)1 << 15)
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#define WL_P2_MASK 0x7f0000 /* pattern 2 */
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#define WL_P2_SHIFT 16
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#define WL_D2 ((uint32)1 << 23)
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#define WL_P3_MASK 0x7f000000 /* pattern 3 */
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#define WL_P3_SHIFT 24
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#define WL_D3 ((uint32)1 << 31)
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/* intstatus and intmask */
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#define I_PME ((uint32)1 << 6) /* power management event */
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#define I_TO ((uint32)1 << 7) /* general purpose timeout */
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#define I_PC ((uint32)1 << 10) /* descriptor error */
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#define I_PD ((uint32)1 << 11) /* data error */
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#define I_DE ((uint32)1 << 12) /* descriptor protocol error */
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#define I_RU ((uint32)1 << 13) /* receive descriptor underflow */
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#define I_RO ((uint32)1 << 14) /* receive fifo overflow */
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#define I_XU ((uint32)1 << 15) /* transmit fifo underflow */
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#define I_RI ((uint32)1 << 16) /* receive interrupt */
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#define I_XI ((uint32)1 << 24) /* transmit interrupt */
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#define I_EM ((uint32)1 << 26) /* emac interrupt */
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#define I_MW ((uint32)1 << 27) /* mii write */
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#define I_MR ((uint32)1 << 28) /* mii read */
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/* emaccontrol */
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#define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */
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#define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
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#define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
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#define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */
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#define EMC_LC_SHIFT 5
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/* emacflowcontrol */
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#define EMF_RFH_MASK 0xff /* rx fifo hi water mark */
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#define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */
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/* interrupt receive lazy */
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#define IRL_TO_MASK 0x00ffffff /* timeout */
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#define IRL_FC_MASK 0xff000000 /* frame count */
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#define IRL_FC_SHIFT 24 /* frame count */
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/* emac receive config */
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#define ERC_DB ((uint32)1 << 0) /* disable broadcast */
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#define ERC_AM ((uint32)1 << 1) /* accept all multicast */
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#define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */
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#define ERC_PE ((uint32)1 << 3) /* promiscuous enable */
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#define ERC_LE ((uint32)1 << 4) /* loopback enable */
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#define ERC_FE ((uint32)1 << 5) /* enable flow control */
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#define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */
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#define ERC_RF ((uint32)1 << 7) /* reject filter */
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/* emac mdio control */
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#define MC_MF_MASK 0x7f /* mdc frequency */
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#define MC_PE ((uint32)1 << 7) /* mii preamble enable */
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/* emac mdio data */
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#define MD_DATA_MASK 0xffff /* r/w data */
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#define MD_TA_MASK 0x30000 /* turnaround value */
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#define MD_TA_SHIFT 16
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#define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */
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#define MD_RA_MASK 0x7c0000 /* register address */
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#define MD_RA_SHIFT 18
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#define MD_PMD_MASK 0xf800000 /* physical media device */
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#define MD_PMD_SHIFT 23
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#define MD_OP_MASK 0x30000000 /* opcode */
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#define MD_OP_SHIFT 28
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#define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */
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#define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */
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#define MD_SB_MASK 0xc0000000 /* start bits */
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#define MD_SB_SHIFT 30
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#define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */
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/* emac intstatus and intmask */
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#define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */
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#define EI_MIB ((uint32)1 << 1) /* mib interrupt */
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#define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */
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/* emac cam data high */
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#define CD_V ((uint32)1 << 16) /* valid bit */
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/* emac cam control */
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#define CC_CE ((uint32)1 << 0) /* cam enable */
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#define CC_MS ((uint32)1 << 1) /* mask select */
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#define CC_RD ((uint32)1 << 2) /* read */
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#define CC_WR ((uint32)1 << 3) /* write */
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#define CC_INDEX_MASK 0x3f0000 /* index */
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#define CC_INDEX_SHIFT 16
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#define CC_CB ((uint32)1 << 31) /* cam busy */
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/* emac ethernet control */
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#define EC_EE ((uint32)1 << 0) /* emac enable */
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#define EC_ED ((uint32)1 << 1) /* emac disable */
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#define EC_ES ((uint32)1 << 2) /* emac soft reset */
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#define EC_EP ((uint32)1 << 3) /* external phy select */
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/* emac transmit control */
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#define EXC_FD ((uint32)1 << 0) /* full duplex */
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#define EXC_FM ((uint32)1 << 1) /* flowmode */
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#define EXC_SB ((uint32)1 << 2) /* single backoff enable */
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#define EXC_SS ((uint32)1 << 3) /* small slottime */
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/* emac mib control */
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#define EMC_RZ ((uint32)1 << 0) /* autoclear on read */
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/* sometimes you just need the enet rxheader definitions */
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#include <bcmenetrxh.h>
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#endif /* _bcmenet_47xx_h_ */
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