mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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b80c50f7cf
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13509 3c298f89-4303-0410-b956-a3cf2f4a3e73
155 lines
3.4 KiB
C
155 lines
3.4 KiB
C
/*
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* Atheros AR71xx SoC GPIO API support
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*
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* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/gpio.h>
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#include <asm/mach-ar71xx/ar71xx.h>
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static DEFINE_SPINLOCK(ar71xx_gpio_lock);
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unsigned long ar71xx_gpio_count;
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EXPORT_SYMBOL(ar71xx_gpio_count);
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void __ar71xx_gpio_set_value(unsigned gpio, int value)
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{
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unsigned long flags;
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spin_lock_irqsave(&ar71xx_gpio_lock, flags);
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if (value)
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ar71xx_gpio_wr(GPIO_REG_SET, (1 << gpio));
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else
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ar71xx_gpio_wr(GPIO_REG_CLEAR, (1 << gpio));
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spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
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}
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EXPORT_SYMBOL(__ar71xx_gpio_set_value);
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int __ar71xx_gpio_get_value(unsigned gpio)
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{
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return (ar71xx_gpio_rr(GPIO_REG_IN) & (1 << gpio)) ? 1 : 0;
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}
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EXPORT_SYMBOL(__ar71xx_gpio_get_value);
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static int ar71xx_gpio_get_value(struct gpio_chip *chip, unsigned offset)
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{
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return __ar71xx_gpio_get_value(offset);
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}
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static void ar71xx_gpio_set_value(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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__ar71xx_gpio_set_value(offset, value);
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}
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static int ar71xx_gpio_direction_input(struct gpio_chip *chip,
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unsigned offset)
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{
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unsigned long flags;
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spin_lock_irqsave(&ar71xx_gpio_lock, flags);
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ar71xx_gpio_wr(GPIO_REG_OE,
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ar71xx_gpio_rr(GPIO_REG_OE) & ~(1 << offset));
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spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
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return 0;
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}
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static int ar71xx_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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unsigned long flags;
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spin_lock_irqsave(&ar71xx_gpio_lock, flags);
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if (value)
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ar71xx_gpio_wr(GPIO_REG_SET, (1 << offset));
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else
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ar71xx_gpio_wr(GPIO_REG_CLEAR, (1 << offset));
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ar71xx_gpio_wr(GPIO_REG_OE,
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ar71xx_gpio_rr(GPIO_REG_OE) | (1 << offset));
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spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
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return 0;
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}
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static struct gpio_chip ar71xx_gpio_chip = {
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.label = "ar71xx",
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.get = ar71xx_gpio_get_value,
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.set = ar71xx_gpio_set_value,
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.direction_input = ar71xx_gpio_direction_input,
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.direction_output = ar71xx_gpio_direction_output,
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.base = 0,
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.ngpio = AR71XX_GPIO_COUNT,
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};
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void ar71xx_gpio_function_enable(u32 mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&ar71xx_gpio_lock, flags);
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ar71xx_gpio_wr(GPIO_REG_FUNC, ar71xx_gpio_rr(GPIO_REG_FUNC) | mask);
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spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
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}
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void ar71xx_gpio_function_disable(u32 mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&ar71xx_gpio_lock, flags);
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ar71xx_gpio_wr(GPIO_REG_FUNC, ar71xx_gpio_rr(GPIO_REG_FUNC) & ~mask);
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spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
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}
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void __init ar71xx_gpio_init(void)
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{
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int err;
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if (!request_mem_region(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
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"AR71xx GPIO controller"))
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panic("cannot allocate AR71xx GPIO registers page");
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7130:
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case AR71XX_SOC_AR7141:
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case AR71XX_SOC_AR7161:
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ar71xx_gpio_chip.ngpio = AR71XX_GPIO_COUNT;
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break;
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case AR71XX_SOC_AR9130:
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case AR71XX_SOC_AR9132:
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ar71xx_gpio_chip.ngpio = AR91XX_GPIO_COUNT;
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break;
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default:
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BUG();
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}
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err = gpiochip_add(&ar71xx_gpio_chip);
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if (err)
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panic("cannot add AR71xx GPIO chip, error=%d", err);
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}
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