mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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796a9d1091
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@15242 3c298f89-4303-0410-b956-a3cf2f4a3e73
237 lines
9.8 KiB
C
237 lines
9.8 KiB
C
/*
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* BCM43XX SiliconBackplane PCIE core hardware definitions.
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*
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* Copyright 2007, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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*/
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#ifndef _SBPCIE_H
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#define _SBPCIE_H
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/* cpp contortions to concatenate w/arg prescan */
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#ifndef PAD
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#define _PADLINE(line) pad ## line
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#define _XSTR(line) _PADLINE(line)
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#define PAD _XSTR(__LINE__)
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#endif
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/* PCIE Enumeration space offsets */
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#define PCIE_CORE_CONFIG_OFFSET 0x0
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#define PCIE_FUNC0_CONFIG_OFFSET 0x400
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#define PCIE_FUNC1_CONFIG_OFFSET 0x500
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#define PCIE_FUNC2_CONFIG_OFFSET 0x600
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#define PCIE_FUNC3_CONFIG_OFFSET 0x700
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#define PCIE_SPROM_SHADOW_OFFSET 0x800
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#define PCIE_SBCONFIG_OFFSET 0xE00
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/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
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#define PCIE_DEV_BAR0_SIZE 0x4000
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#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
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#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
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#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
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#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
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/* different register spaces to access thr'u pcie indirect access */
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#define PCIE_CONFIGREGS 1 /* Access to config space */
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#define PCIE_PCIEREGS 2 /* Access to pcie registers */
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/* SB side: PCIE core and host control registers */
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typedef struct sbpcieregs {
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uint32 PAD[3];
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uint32 biststatus; /* bist Status: 0x00C */
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uint32 gpiosel; /* PCIE gpio sel: 0x010 */
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uint32 gpioouten; /* PCIE gpio outen: 0x14 */
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uint32 PAD[4];
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uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
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uint32 PAD[54];
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uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
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uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
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uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
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uint32 PAD[4];
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/* pcie core supports in direct access to config space */
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uint32 configaddr; /* pcie config space access: Address field: 0x120 */
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uint32 configdata; /* pcie config space access: Data field: 0x124 */
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/* mdio access to serdes */
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uint32 mdiocontrol; /* controls the mdio access: 0x128 */
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uint32 mdiodata; /* Data to the mdio access: 0x12c */
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/* pcie protocol phy/dllp/tlp register indirect access mechanism */
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uint32 pcieindaddr; /* indirect access to the internal register: 0x130 */
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uint32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */
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uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */
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uint32 PAD[433];
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uint16 sprom[36]; /* SPROM shadow Area */
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} sbpcieregs_t;
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/* SB to PCIE translation masks */
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#define SBTOPCIE0_MASK 0xfc000000
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#define SBTOPCIE1_MASK 0xfc000000
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#define SBTOPCIE2_MASK 0xc0000000
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/* Access type bits (0:1) */
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#define SBTOPCIE_MEM 0
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#define SBTOPCIE_IO 1
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#define SBTOPCIE_CFG0 2
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#define SBTOPCIE_CFG1 3
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/* Prefetch enable bit 2 */
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#define SBTOPCIE_PF 4
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/* Write Burst enable for memory write bit 3 */
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#define SBTOPCIE_WR_BURST 8
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/* config access */
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#define CONFIGADDR_FUNC_MASK 0x7000
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#define CONFIGADDR_FUNC_SHF 12
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#define CONFIGADDR_REG_MASK 0x0FFF
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#define CONFIGADDR_REG_SHF 0
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/* PCIE protocol regs Indirect Address */
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#define PCIEADDR_PROT_MASK 0x300
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#define PCIEADDR_PROT_SHF 8
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#define PCIEADDR_PL_TLP 0
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#define PCIEADDR_PL_DLLP 1
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#define PCIEADDR_PL_PLP 2
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/* PCIE protocol PHY diagnostic registers */
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#define PCIE_PLP_MODEREG 0x200 /* Mode */
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#define PCIE_PLP_STATUSREG 0x204 /* Status */
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#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
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#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
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#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
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#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
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#define PCIE_PLP_ATTNREG 0x218 /* Attention */
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#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
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#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
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#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
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#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
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#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */
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#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
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#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
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#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
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#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
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/* PCIE protocol DLLP diagnostic registers */
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#define PCIE_DLLP_LCREG 0x100 /* Link Control */
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#define PCIE_DLLP_LSREG 0x104 /* Link Status */
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#define PCIE_DLLP_LAREG 0x108 /* Link Attention */
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#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
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#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
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#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
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#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
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#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
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#define PCIE_DLLP_LRREG 0x120 /* Link Replay */
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#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
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#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
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#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
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#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
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#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
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#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
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#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
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#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
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#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */
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#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
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#define PCIE_DLLP_TESTREG 0x14C /* Test */
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#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */
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#define PCIE_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
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/* PCIE protocol TLP diagnostic registers */
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#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
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#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
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#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */
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#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */
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#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */
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#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */
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#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */
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#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */
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#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */
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#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */
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#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */
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#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */
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#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */
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#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */
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#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */
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#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */
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#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */
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#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */
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#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
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#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
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#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
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#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */
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#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */
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#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */
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#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */
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#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter */
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#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */
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#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */
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#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */
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#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */
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#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */
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/* MDIO control */
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#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
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#define MDIOCTL_DIVISOR_VAL 0x2
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#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
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#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
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/* MDIO Data */
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#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
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#define MDIODATA_TA 0x00020000 /* Turnaround */
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#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
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#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
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#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
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#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
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#define MDIODATA_WRITE 0x10000000 /* write Transaction */
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#define MDIODATA_READ 0x20000000 /* Read Transaction */
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#define MDIODATA_START 0x40000000 /* start of Transaction */
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/* MDIO devices (SERDES modules) */
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#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
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#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
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#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
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/* SERDES RX registers */
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#define SERDES_RX_CTRL 1 /* Rx cntrl */
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#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
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#define SERDES_RX_CDR 6 /* CDR */
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#define SERDES_RX_CDRBW 7 /* CDR BW */
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/* SERDES RX control register */
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#define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
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#define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
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/* SERDES PLL registers */
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#define SERDES_PLL_CTRL 1 /* PLL control reg */
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#define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
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#define PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */
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#define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */
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#define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */
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/* SPROM offsets */
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#define SRSH_ASPM_OFFSET 4 /* word 4 */
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#define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */
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#define SRSH_CLKREQ_OFFSET 20 /* word 20 */
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#define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */
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/* Linkcontrol reg offset in PCIE Cap */
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#define PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */
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#define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */
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#define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */
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#define PCIE_ASPM_ENAB 0x03 /* ASPM L0s & L1 in linkctrl */
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#define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */
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/* Status reg PCIE_PLP_STATUSREG */
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#define PCIE_PLP_POLARITYINV_STAT 0x10
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#endif /* _SBPCIE_H */
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