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08b17128a1
use {read,write}l_relaxed instead of the plain __raw_{read,write}l variants.
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33330 3c298f89-4303-0410-b956-a3cf2f4a3e73
70 lines
1.6 KiB
C
70 lines
1.6 KiB
C
/*
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* Moschip MCS814x generic interrupt controller routines
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*
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* Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
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*
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* Licensed under the GPLv2
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/irqdomain.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#include <mach/mcs814x.h>
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void __iomem *mcs814x_intc_base;
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static void __init mcs814x_alloc_gc(void __iomem *base, unsigned int irq_start,
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unsigned int num)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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gc = irq_alloc_generic_chip("mcs814x-intc", 1,
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irq_start, base, handle_level_irq);
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if (!gc)
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panic("unable to allocate generic irq chip");
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ct = gc->chip_types;
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ct->chip.irq_ack = irq_gc_unmask_enable_reg;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->regs.mask = MCS814X_IRQ_MASK;
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ct->regs.enable = MCS814X_IRQ_ICR;
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irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST, 0);
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/* Clear all interrupts */
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writel_relaxed(0xffffffff, base + MCS814X_IRQ_ICR);
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}
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static const struct of_device_id mcs814x_intc_ids[] = {
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{ .compatible = "moschip,mcs814x-intc" },
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{ /* sentinel */ },
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};
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void __init mcs814x_of_irq_init(void)
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{
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struct device_node *np;
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np = of_find_matching_node(NULL, mcs814x_intc_ids);
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if (!np)
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panic("unable to find compatible intc node in dtb\n");
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mcs814x_intc_base = of_iomap(np, 0);
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if (!mcs814x_intc_base)
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panic("unable to map intc cpu registers\n");
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irq_domain_add_simple(np, 0);
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of_node_put(np);
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mcs814x_alloc_gc(mcs814x_intc_base, 0, 32);
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}
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