mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 13:38:04 +03:00
Add missing external IRQ code parts for older chips in the new code. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31128 3c298f89-4303-0410-b956-a3cf2f4a3e73
905 lines
24 KiB
Diff
905 lines
24 KiB
Diff
--- /dev/null
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+++ b/arch/mips/bcm63xx/dev-spi.c
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@@ -0,0 +1,99 @@
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+/*
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+ * This file is subject to the terms and conditions of the GNU General Public
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+ * License. See the file "COPYING" in the main directory of this archive
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+ * for more details.
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+ *
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+ * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org>
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+ * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/kernel.h>
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+#include <linux/platform_device.h>
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+#include <linux/export.h>
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+
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+#include <bcm63xx_cpu.h>
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+#include <bcm63xx_dev_spi.h>
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+#include <bcm63xx_regs.h>
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+
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+#ifdef BCMCPU_RUNTIME_DETECT
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+/*
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+ * register offsets
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+ */
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+static const unsigned long bcm96338_regs_spi[] = {
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+ __GEN_SPI_REGS_TABLE(6338)
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+};
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+
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+static const unsigned long bcm96348_regs_spi[] = {
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+ __GEN_SPI_REGS_TABLE(6348)
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+};
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+
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+static const unsigned long bcm96358_regs_spi[] = {
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+ __GEN_SPI_REGS_TABLE(6358)
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+};
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+
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+const unsigned long *bcm63xx_regs_spi;
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+EXPORT_SYMBOL(bcm63xx_regs_spi);
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+
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+static __init void bcm63xx_spi_regs_init(void)
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+{
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+ if (BCMCPU_IS_6338())
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+ bcm63xx_regs_spi = bcm96338_regs_spi;
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+ if (BCMCPU_IS_6348())
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+ bcm63xx_regs_spi = bcm96348_regs_spi;
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+ if (BCMCPU_IS_6358())
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+ bcm63xx_regs_spi = bcm96358_regs_spi;
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+}
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+#else
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+static __init void bcm63xx_spi_regs_init(void) { }
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+#endif
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+
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+static struct resource spi_resources[] = {
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+ {
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+ .start = -1, /* filled at runtime */
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+ .end = -1, /* filled at runtime */
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .start = -1, /* filled at runtime */
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static struct bcm63xx_spi_pdata spi_pdata = {
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+ .bus_num = 0,
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+ .num_chipselect = 8,
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+ .speed_hz = 50000000, /* Fclk */
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+};
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+
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+static struct platform_device bcm63xx_spi_device = {
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+ .name = "bcm63xx-spi",
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+ .id = 0,
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+ .num_resources = ARRAY_SIZE(spi_resources),
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+ .resource = spi_resources,
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+ .dev = {
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+ .platform_data = &spi_pdata,
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+ },
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+};
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+
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+int __init bcm63xx_spi_register(void)
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+{
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+ spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
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+ spi_resources[0].end = spi_resources[0].start;
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+ spi_resources[0].end += RSET_SPI_SIZE - 1;
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+ spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
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+
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+ if (BCMCPU_IS_6345())
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+ return -ENODEV;
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+
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+ /* Fill in platform data */
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+ if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
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+ spi_pdata.fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
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+
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+ if (BCMCPU_IS_6358())
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+ spi_pdata.fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
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+
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+ bcm63xx_spi_regs_init();
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+
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+ return platform_device_register(&bcm63xx_spi_device);
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+}
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -138,6 +138,7 @@ enum bcm63xx_regs_set {
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#define RSET_ENET_SIZE 2048
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#define RSET_ENETDMA_SIZE 2048
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#define RSET_ENETSW_SIZE 65536
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+#define RSET_SPI_SIZE 256
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#define RSET_UART_SIZE 24
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#define RSET_UDC_SIZE 256
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#define RSET_OHCI_SIZE 256
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@@ -289,7 +290,7 @@ enum bcm63xx_regs_set {
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#define BCM_6358_UART0_BASE (0xfffe0100)
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#define BCM_6358_UART1_BASE (0xfffe0120)
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#define BCM_6358_GPIO_BASE (0xfffe0080)
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-#define BCM_6358_SPI_BASE (0xdeadbeef)
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+#define BCM_6358_SPI_BASE (0xfffe0800)
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#define BCM_6358_SPI2_BASE (0xfffe0800)
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#define BCM_6358_UDC0_BASE (0xfffe0800)
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#define BCM_6358_OHCI0_BASE (0xfffe1400)
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@@ -478,6 +479,7 @@ static inline unsigned long bcm63xx_regs
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*/
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enum bcm63xx_irq {
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IRQ_TIMER = 0,
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+ IRQ_SPI,
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IRQ_UART0,
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IRQ_UART1,
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IRQ_DSL,
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@@ -569,6 +571,7 @@ enum bcm63xx_irq {
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* 6348 irqs
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*/
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#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
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+#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
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#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
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#define BCM_6348_UART1_IRQ 0
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#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
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@@ -599,6 +602,7 @@ enum bcm63xx_irq {
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* 6358 irqs
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*/
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#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
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+#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
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#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
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#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
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#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -1008,4 +1008,116 @@
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#define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
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#define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
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+/*************************************************************************
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+ * _REG relative to RSET_SPI
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+ *************************************************************************/
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+
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+/* BCM 6338 SPI core */
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+#define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */
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+#define SPI_BCM_6338_SPI_INT_STATUS 0x02
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+#define SPI_BCM_6338_SPI_INT_MASK_ST 0x03
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+#define SPI_BCM_6338_SPI_INT_MASK 0x04
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+#define SPI_BCM_6338_SPI_ST 0x05
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+#define SPI_BCM_6338_SPI_CLK_CFG 0x06
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+#define SPI_BCM_6338_SPI_FILL_BYTE 0x07
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+#define SPI_BCM_6338_SPI_MSG_TAIL 0x09
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+#define SPI_BCM_6338_SPI_RX_TAIL 0x0b
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+#define SPI_BCM_6338_SPI_MSG_CTL 0x40
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+#define SPI_BCM_6338_SPI_MSG_DATA 0x41
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+#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
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+#define SPI_BCM_6338_SPI_RX_DATA 0x80
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+#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
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+
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+/* BCM 6348 SPI core */
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+#define SPI_BCM_6348_SPI_CMD 0x00 /* 16-bits register */
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+#define SPI_BCM_6348_SPI_INT_STATUS 0x02
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+#define SPI_BCM_6348_SPI_INT_MASK_ST 0x03
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+#define SPI_BCM_6348_SPI_INT_MASK 0x04
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+#define SPI_BCM_6348_SPI_ST 0x05
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+#define SPI_BCM_6348_SPI_CLK_CFG 0x06
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+#define SPI_BCM_6348_SPI_FILL_BYTE 0x07
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+#define SPI_BCM_6348_SPI_MSG_TAIL 0x09
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+#define SPI_BCM_6348_SPI_RX_TAIL 0x0b
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+#define SPI_BCM_6348_SPI_MSG_CTL 0x40
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+#define SPI_BCM_6348_SPI_MSG_DATA 0x41
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+#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
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+#define SPI_BCM_6348_SPI_RX_DATA 0x80
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+#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
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+
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+/* BCM 6358 SPI core */
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+#define SPI_BCM_6358_SPI_MSG_CTL 0x00 /* 16-bits register */
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+
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+#define SPI_BCM_6358_SPI_MSG_DATA 0x02
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+#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
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+
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+#define SPI_BCM_6358_SPI_RX_DATA 0x400
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+#define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220
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+
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+#define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
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+
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+#define SPI_BCM_6358_SPI_INT_STATUS 0x702
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+#define SPI_BCM_6358_SPI_INT_MASK_ST 0x703
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+
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+#define SPI_BCM_6358_SPI_INT_MASK 0x704
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+
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+#define SPI_BCM_6358_SPI_ST 0x705
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+
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+#define SPI_BCM_6358_SPI_CLK_CFG 0x706
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+
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+#define SPI_BCM_6358_SPI_FILL_BYTE 0x707
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+#define SPI_BCM_6358_SPI_MSG_TAIL 0x709
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+#define SPI_BCM_6358_SPI_RX_TAIL 0x70B
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+
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+/* Shared SPI definitions */
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+
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+/* Message configuration */
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+#define SPI_FD_RW 0x00
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+#define SPI_HD_W 0x01
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+#define SPI_HD_R 0x02
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+#define SPI_BYTE_CNT_SHIFT 0
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+#define SPI_MSG_TYPE_SHIFT 14
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+
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+/* Command */
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+#define SPI_CMD_NOOP 0x00
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+#define SPI_CMD_SOFT_RESET 0x01
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+#define SPI_CMD_HARD_RESET 0x02
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+#define SPI_CMD_START_IMMEDIATE 0x03
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+#define SPI_CMD_COMMAND_SHIFT 0
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+#define SPI_CMD_COMMAND_MASK 0x000f
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+#define SPI_CMD_DEVICE_ID_SHIFT 4
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+#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
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+#define SPI_CMD_ONE_BYTE_SHIFT 11
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+#define SPI_CMD_ONE_WIRE_SHIFT 12
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+#define SPI_DEV_ID_0 0
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+#define SPI_DEV_ID_1 1
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+#define SPI_DEV_ID_2 2
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+#define SPI_DEV_ID_3 3
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+
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+/* Interrupt mask */
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+#define SPI_INTR_CMD_DONE 0x01
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+#define SPI_INTR_RX_OVERFLOW 0x02
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+#define SPI_INTR_TX_UNDERFLOW 0x04
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+#define SPI_INTR_TX_OVERFLOW 0x08
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+#define SPI_INTR_RX_UNDERFLOW 0x10
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+#define SPI_INTR_CLEAR_ALL 0x1f
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+
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+/* Status */
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+#define SPI_RX_EMPTY 0x02
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+#define SPI_CMD_BUSY 0x04
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+#define SPI_SERIAL_BUSY 0x08
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+
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+/* Clock configuration */
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+#define SPI_CLK_20MHZ 0x00
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+#define SPI_CLK_0_391MHZ 0x01
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+#define SPI_CLK_0_781MHZ 0x02 /* default */
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+#define SPI_CLK_1_563MHZ 0x03
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+#define SPI_CLK_3_125MHZ 0x04
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+#define SPI_CLK_6_250MHZ 0x05
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+#define SPI_CLK_12_50MHZ 0x06
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+#define SPI_CLK_25MHZ 0x07
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+#define SPI_CLK_MASK 0x07
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+#define SPI_SSOFFTIME_MASK 0x38
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+#define SPI_SSOFFTIME_SHIFT 3
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+#define SPI_BYTE_SWAP 0x80
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+
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#endif /* BCM63XX_REGS_H_ */
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--- /dev/null
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+++ b/drivers/spi/bcm63xx_spi.c
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@@ -0,0 +1,496 @@
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+/*
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+ * Broadcom BCM63xx SPI controller support
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+ *
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+ * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
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+ * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License
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+ * as published by the Free Software Foundation; either version 2
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+ * of the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the
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+ * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/clk.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/delay.h>
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+#include <linux/interrupt.h>
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+#include <linux/spi/spi.h>
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+#include <linux/completion.h>
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+#include <linux/err.h>
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+
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+#include <bcm63xx_dev_spi.h>
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+
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+#define PFX KBUILD_MODNAME
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+#define DRV_VER "0.1.2"
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+
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+struct bcm63xx_spi {
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+ spinlock_t lock;
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+ int stopping;
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+ struct completion done;
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+
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+ void __iomem *regs;
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+ int irq;
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+
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+ /* Platform data */
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+ u32 speed_hz;
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+ unsigned fifo_size;
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+
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+ /* Data buffers */
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+ const unsigned char *tx_ptr;
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+ unsigned char *rx_ptr;
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+
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+ /* data iomem */
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+ u8 __iomem *tx_io;
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+ const u8 __iomem *rx_io;
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+
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+ int remaining_bytes;
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+
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+ struct clk *clk;
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+ struct platform_device *pdev;
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+};
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+
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+static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
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+ unsigned int offset)
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+{
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+ return bcm_readw(bs->regs + bcm63xx_spireg(offset));
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+}
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+
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+static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
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+ unsigned int offset)
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+{
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+ return bcm_readw(bs->regs + bcm63xx_spireg(offset));
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+}
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+
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+static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
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+ u8 value, unsigned int offset)
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+{
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+ bcm_writeb(value, bs->regs + bcm63xx_spireg(offset));
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+}
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+
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+static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
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+ u16 value, unsigned int offset)
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+{
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+ bcm_writew(value, bs->regs + bcm63xx_spireg(offset));
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+}
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+
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+static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
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+ struct spi_transfer *t)
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+{
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+ u8 bits_per_word;
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+ u8 clk_cfg;
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+ u32 hz;
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+ unsigned int div;
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+
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+ struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
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+
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+ bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
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+ hz = (t) ? t->speed_hz : spi->max_speed_hz;
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+ if (bits_per_word != 8) {
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+ dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
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+ __func__, bits_per_word);
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+ return -EINVAL;
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+ }
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+
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+ if (spi->chip_select > spi->master->num_chipselect) {
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+ dev_err(&spi->dev, "%s, unsupported slave %d\n",
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+ __func__, spi->chip_select);
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+ return -EINVAL;
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+ }
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+
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+ /* Check clock setting */
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+ div = (bs->speed_hz / hz);
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+ switch (div) {
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+ case 2:
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+ clk_cfg = SPI_CLK_25MHZ;
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+ break;
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+ case 4:
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+ clk_cfg = SPI_CLK_12_50MHZ;
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+ break;
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+ case 8:
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+ clk_cfg = SPI_CLK_6_250MHZ;
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+ break;
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+ case 16:
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+ clk_cfg = SPI_CLK_3_125MHZ;
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+ break;
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+ case 32:
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+ clk_cfg = SPI_CLK_1_563MHZ;
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+ break;
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+ case 64:
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+ clk_cfg = SPI_CLK_0_781MHZ;
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+ break;
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+ case 128:
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+ default:
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+ /* Set to slowest mode for compatibility */
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+ clk_cfg = SPI_CLK_0_391MHZ;
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+ break;
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+ }
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+
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+ bcm_spi_writeb(bs, clk_cfg, SPI_CLK_CFG);
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+ dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
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+ div, hz, clk_cfg);
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+
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+ return 0;
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+}
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+
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+/* the spi->mode bits understood by this driver: */
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+#define MODEBITS (SPI_CPOL | SPI_CPHA)
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+
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+static int bcm63xx_spi_setup(struct spi_device *spi)
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+{
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+ struct bcm63xx_spi *bs;
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+ int ret;
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+
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+ bs = spi_master_get_devdata(spi->master);
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+
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+ if (bs->stopping)
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+ return -ESHUTDOWN;
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+
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+ if (!spi->bits_per_word)
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+ spi->bits_per_word = 8;
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|
+
|
|
+ if (spi->mode & ~MODEBITS) {
|
|
+ dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
|
|
+ __func__, spi->mode & ~MODEBITS);
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ ret = bcm63xx_spi_setup_transfer(spi, NULL);
|
|
+ if (ret < 0) {
|
|
+ dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
|
|
+ spi->mode & ~MODEBITS);
|
|
+ return ret;
|
|
+ }
|
|
+
|
|
+ dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
|
|
+ __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/* Fill the TX FIFO with as many bytes as possible */
|
|
+static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
|
|
+{
|
|
+ u8 size;
|
|
+
|
|
+ /* Fill the Tx FIFO with as many bytes as possible */
|
|
+ size = bs->remaining_bytes < bs->fifo_size ? bs->remaining_bytes :
|
|
+ bs->fifo_size;
|
|
+ memcpy_toio(bs->tx_io, bs->tx_ptr, size);
|
|
+ bs->remaining_bytes -= size;
|
|
+}
|
|
+
|
|
+static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
|
|
+{
|
|
+ struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
|
|
+ u16 msg_ctl;
|
|
+ u16 cmd;
|
|
+
|
|
+ dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
|
|
+ t->tx_buf, t->rx_buf, t->len);
|
|
+
|
|
+ /* Transmitter is inhibited */
|
|
+ bs->tx_ptr = t->tx_buf;
|
|
+ bs->rx_ptr = t->rx_buf;
|
|
+ init_completion(&bs->done);
|
|
+
|
|
+ if (t->tx_buf) {
|
|
+ bs->remaining_bytes = t->len;
|
|
+ bcm63xx_spi_fill_tx_fifo(bs);
|
|
+ }
|
|
+
|
|
+ /* Enable the command done interrupt which
|
|
+ * we use to determine completion of a command */
|
|
+ bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
|
|
+
|
|
+ /* Fill in the Message control register */
|
|
+ msg_ctl = (t->len << SPI_BYTE_CNT_SHIFT);
|
|
+
|
|
+ if (t->rx_buf && t->tx_buf)
|
|
+ msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
|
|
+ else if (t->rx_buf)
|
|
+ msg_ctl |= (SPI_HD_R << SPI_MSG_TYPE_SHIFT);
|
|
+ else if (t->tx_buf)
|
|
+ msg_ctl |= (SPI_HD_W << SPI_MSG_TYPE_SHIFT);
|
|
+
|
|
+ bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
|
|
+
|
|
+ /* Issue the transfer */
|
|
+ cmd = SPI_CMD_START_IMMEDIATE;
|
|
+ cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
|
|
+ cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
|
|
+ bcm_spi_writew(bs, cmd, SPI_CMD);
|
|
+ wait_for_completion(&bs->done);
|
|
+
|
|
+ /* Disable the CMD_DONE interrupt */
|
|
+ bcm_spi_writeb(bs, 0, SPI_INT_MASK);
|
|
+
|
|
+ return t->len - bs->remaining_bytes;
|
|
+}
|
|
+
|
|
+static int bcm63xx_transfer(struct spi_device *spi, struct spi_message *m)
|
|
+{
|
|
+ struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
|
|
+ struct spi_transfer *t;
|
|
+ int ret = 0;
|
|
+
|
|
+ if (unlikely(list_empty(&m->transfers)))
|
|
+ return -EINVAL;
|
|
+
|
|
+ if (bs->stopping)
|
|
+ return -ESHUTDOWN;
|
|
+
|
|
+ list_for_each_entry(t, &m->transfers, transfer_list) {
|
|
+ ret += bcm63xx_txrx_bufs(spi, t);
|
|
+ }
|
|
+
|
|
+ m->complete(m->context);
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+/* This driver supports single master mode only. Hence
|
|
+ * CMD_DONE is the only interrupt we care about
|
|
+ */
|
|
+static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
|
|
+{
|
|
+ struct spi_master *master = (struct spi_master *)dev_id;
|
|
+ struct bcm63xx_spi *bs = spi_master_get_devdata(master);
|
|
+ u8 intr;
|
|
+ u16 cmd;
|
|
+
|
|
+ /* Read interupts and clear them immediately */
|
|
+ intr = bcm_spi_readb(bs, SPI_INT_STATUS);
|
|
+ bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
|
|
+ bcm_spi_writeb(bs, 0, SPI_INT_MASK);
|
|
+
|
|
+ /* A tansfer completed */
|
|
+ if (intr & SPI_INTR_CMD_DONE) {
|
|
+ u8 rx_tail;
|
|
+
|
|
+ rx_tail = bcm_spi_readb(bs, SPI_RX_TAIL);
|
|
+
|
|
+ /* Read out all the data */
|
|
+ if (rx_tail)
|
|
+ memcpy_fromio(bs->rx_ptr, bs->rx_io, rx_tail);
|
|
+
|
|
+ /* See if there is more data to send */
|
|
+ if (bs->remaining_bytes > 0) {
|
|
+ bcm63xx_spi_fill_tx_fifo(bs);
|
|
+
|
|
+ /* Start the transfer */
|
|
+ bcm_spi_writew(bs, SPI_HD_W << SPI_MSG_TYPE_SHIFT,
|
|
+ SPI_MSG_CTL);
|
|
+ cmd = bcm_spi_readw(bs, SPI_CMD);
|
|
+ cmd |= SPI_CMD_START_IMMEDIATE;
|
|
+ cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
|
|
+ bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
|
|
+ bcm_spi_writew(bs, cmd, SPI_CMD);
|
|
+ } else {
|
|
+ complete(&bs->done);
|
|
+ }
|
|
+ }
|
|
+
|
|
+ return IRQ_HANDLED;
|
|
+}
|
|
+
|
|
+
|
|
+static int __init bcm63xx_spi_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct resource *r;
|
|
+ struct device *dev = &pdev->dev;
|
|
+ struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
|
|
+ int irq;
|
|
+ struct spi_master *master;
|
|
+ struct clk *clk;
|
|
+ struct bcm63xx_spi *bs;
|
|
+ int ret;
|
|
+
|
|
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
+ if (!r) {
|
|
+ dev_err(dev, "no iomem\n");
|
|
+ ret = -ENXIO;
|
|
+ goto out;
|
|
+ }
|
|
+
|
|
+ irq = platform_get_irq(pdev, 0);
|
|
+ if (irq < 0) {
|
|
+ dev_err(dev, "no irq\n");
|
|
+ ret = -ENXIO;
|
|
+ goto out;
|
|
+ }
|
|
+
|
|
+ clk = clk_get(dev, "spi");
|
|
+ if (IS_ERR(clk)) {
|
|
+ dev_err(dev, "no clock for device\n");
|
|
+ ret = -ENODEV;
|
|
+ goto out;
|
|
+ }
|
|
+
|
|
+ master = spi_alloc_master(dev, sizeof(*bs));
|
|
+ if (!master) {
|
|
+ dev_err(dev, "out of memory\n");
|
|
+ ret = -ENOMEM;
|
|
+ goto out_free;
|
|
+ }
|
|
+
|
|
+ bs = spi_master_get_devdata(master);
|
|
+ init_completion(&bs->done);
|
|
+
|
|
+ platform_set_drvdata(pdev, master);
|
|
+ bs->pdev = pdev;
|
|
+
|
|
+ if (!request_mem_region(r->start, r->end - r->start, PFX)) {
|
|
+ dev_err(dev, "iomem request failed\n");
|
|
+ ret = -ENXIO;
|
|
+ goto out_put_master;
|
|
+ }
|
|
+
|
|
+ bs->regs = ioremap_nocache(r->start, r->end - r->start);
|
|
+ if (!bs->regs) {
|
|
+ dev_err(dev, "unable to ioremap regs\n");
|
|
+ ret = -ENOMEM;
|
|
+ goto out_put_master;
|
|
+ }
|
|
+ bs->irq = irq;
|
|
+ bs->clk = clk;
|
|
+ bs->fifo_size = pdata->fifo_size;
|
|
+
|
|
+ ret = request_irq(irq, bcm63xx_spi_interrupt, 0, pdev->name, master);
|
|
+ if (ret) {
|
|
+ dev_err(dev, "unable to request irq\n");
|
|
+ goto out_unmap;
|
|
+ }
|
|
+
|
|
+ master->bus_num = pdata->bus_num;
|
|
+ master->num_chipselect = pdata->num_chipselect;
|
|
+ master->setup = bcm63xx_spi_setup;
|
|
+ master->transfer = bcm63xx_transfer;
|
|
+ bs->speed_hz = pdata->speed_hz;
|
|
+ bs->stopping = 0;
|
|
+ bs->tx_io = (u8*)(bs->regs + bcm63xx_spireg(SPI_MSG_DATA));
|
|
+ bs->rx_io = (const u8*)(bs->regs + bcm63xx_spireg(SPI_RX_DATA));
|
|
+ spin_lock_init(&bs->lock);
|
|
+
|
|
+ /* Initialize hardware */
|
|
+ clk_enable(bs->clk);
|
|
+ bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
|
|
+
|
|
+ /* register and we are done */
|
|
+ ret = spi_register_master(master);
|
|
+ if (ret) {
|
|
+ dev_err(dev, "spi register failed\n");
|
|
+ goto out_reset_hw;
|
|
+ }
|
|
+
|
|
+ dev_info(dev, "at 0x%08x (irq %d, FIFOs size %d) v%s\n",
|
|
+ r->start, irq, bs->fifo_size, DRV_VER);
|
|
+
|
|
+ return 0;
|
|
+
|
|
+out_reset_hw:
|
|
+ clk_disable(clk);
|
|
+ free_irq(irq, master);
|
|
+out_unmap:
|
|
+ iounmap(bs->regs);
|
|
+out_put_master:
|
|
+ spi_master_put(master);
|
|
+out_free:
|
|
+ clk_put(clk);
|
|
+out:
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
|
|
+{
|
|
+ struct spi_master *master = platform_get_drvdata(pdev);
|
|
+ struct bcm63xx_spi *bs = spi_master_get_devdata(master);
|
|
+ struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
+
|
|
+ /* reset spi block */
|
|
+ bcm_spi_writeb(bs, 0, SPI_INT_MASK);
|
|
+ spin_lock(&bs->lock);
|
|
+ bs->stopping = 1;
|
|
+
|
|
+ /* HW shutdown */
|
|
+ clk_disable(bs->clk);
|
|
+ clk_put(bs->clk);
|
|
+
|
|
+ spin_unlock(&bs->lock);
|
|
+
|
|
+ free_irq(bs->irq, master);
|
|
+ iounmap(bs->regs);
|
|
+ release_mem_region(r->start, r->end - r->start);
|
|
+ platform_set_drvdata(pdev, 0);
|
|
+ spi_unregister_master(master);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_PM
|
|
+static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
|
|
+{
|
|
+ struct spi_master *master = platform_get_drvdata(pdev);
|
|
+ struct bcm63xx_spi *bs = spi_master_get_devdata(master);
|
|
+
|
|
+ clk_disable(bs->clk);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int bcm63xx_spi_resume(struct platform_device *pdev)
|
|
+{
|
|
+ struct spi_master *master = platform_get_drvdata(pdev);
|
|
+ struct bcm63xx_spi *bs = spi_master_get_devdata(master);
|
|
+
|
|
+ clk_enable(bs->clk);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+#else
|
|
+#define bcm63xx_spi_suspend NULL
|
|
+#define bcm63xx_spi_resume NULL
|
|
+#endif
|
|
+
|
|
+static struct platform_driver bcm63xx_spi_driver = {
|
|
+ .driver = {
|
|
+ .name = "bcm63xx-spi",
|
|
+ .owner = THIS_MODULE,
|
|
+ },
|
|
+ .probe = bcm63xx_spi_probe,
|
|
+ .remove = __exit_p(bcm63xx_spi_remove),
|
|
+ .suspend = bcm63xx_spi_suspend,
|
|
+ .resume = bcm63xx_spi_resume,
|
|
+};
|
|
+
|
|
+
|
|
+static int __init bcm63xx_spi_init(void)
|
|
+{
|
|
+ return platform_driver_register(&bcm63xx_spi_driver);
|
|
+}
|
|
+
|
|
+static void __exit bcm63xx_spi_exit(void)
|
|
+{
|
|
+ platform_driver_unregister(&bcm63xx_spi_driver);
|
|
+}
|
|
+
|
|
+module_init(bcm63xx_spi_init);
|
|
+module_exit(bcm63xx_spi_exit);
|
|
+
|
|
+MODULE_ALIAS("platform:bcm63xx_spi");
|
|
+MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
|
|
+MODULE_AUTHOR("Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>");
|
|
+MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
|
|
+MODULE_LICENSE("GPL");
|
|
+MODULE_VERSION(DRV_VER);
|
|
--- a/drivers/spi/Kconfig
|
|
+++ b/drivers/spi/Kconfig
|
|
@@ -74,6 +74,12 @@ config SPI_ATMEL
|
|
This selects a driver for the Atmel SPI Controller, present on
|
|
many AT32 (AVR32) and AT91 (ARM) chips.
|
|
|
|
+config SPI_BCM63XX
|
|
+ tristate "Broadcom BCM63xx SPI controller"
|
|
+ depends on BCM63XX
|
|
+ help
|
|
+ This is the SPI controller master driver for Broadcom BCM63xx SoC.
|
|
+
|
|
config SPI_BFIN
|
|
tristate "SPI controller driver for ADI Blackfin5xx"
|
|
depends on BLACKFIN
|
|
--- a/drivers/spi/Makefile
|
|
+++ b/drivers/spi/Makefile
|
|
@@ -14,6 +14,7 @@ obj-$(CONFIG_SPI_ALTERA) += spi-altera.
|
|
obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
|
|
obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
|
|
obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
|
|
+obj-$(CONFIG_SPI_BCM63XX) += bcm63xx_spi.o
|
|
obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o
|
|
obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
|
|
obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
|
|
--- /dev/null
|
|
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
|
|
@@ -0,0 +1,85 @@
|
|
+#ifndef BCM63XX_DEV_SPI_H
|
|
+#define BCM63XX_DEV_SPI_H
|
|
+
|
|
+#include <linux/types.h>
|
|
+#include <bcm63xx_io.h>
|
|
+#include <bcm63xx_regs.h>
|
|
+
|
|
+int __init bcm63xx_spi_register(void);
|
|
+
|
|
+struct bcm63xx_spi_pdata {
|
|
+ unsigned int fifo_size;
|
|
+ int bus_num;
|
|
+ int num_chipselect;
|
|
+ u32 speed_hz;
|
|
+};
|
|
+
|
|
+enum bcm63xx_regs_spi {
|
|
+ SPI_CMD,
|
|
+ SPI_INT_STATUS,
|
|
+ SPI_INT_MASK_ST,
|
|
+ SPI_INT_MASK,
|
|
+ SPI_ST,
|
|
+ SPI_CLK_CFG,
|
|
+ SPI_FILL_BYTE,
|
|
+ SPI_MSG_TAIL,
|
|
+ SPI_RX_TAIL,
|
|
+ SPI_MSG_CTL,
|
|
+ SPI_MSG_DATA,
|
|
+ SPI_RX_DATA,
|
|
+};
|
|
+
|
|
+#define __GEN_SPI_RSET_BASE(__cpu, __rset) \
|
|
+ case SPI_## __rset: \
|
|
+ return SPI_BCM_## __cpu ##_SPI_## __rset;
|
|
+
|
|
+#define __GEN_SPI_RSET(__cpu) \
|
|
+ switch (reg) { \
|
|
+ __GEN_SPI_RSET_BASE(__cpu, CMD) \
|
|
+ __GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \
|
|
+ __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \
|
|
+ __GEN_SPI_RSET_BASE(__cpu, INT_MASK) \
|
|
+ __GEN_SPI_RSET_BASE(__cpu, ST) \
|
|
+ __GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \
|
|
+ __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \
|
|
+ __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \
|
|
+ __GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \
|
|
+ __GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \
|
|
+ __GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \
|
|
+ __GEN_SPI_RSET_BASE(__cpu, RX_DATA) \
|
|
+ }
|
|
+
|
|
+#define __GEN_SPI_REGS_TABLE(__cpu) \
|
|
+ [SPI_CMD] = SPI_BCM_## __cpu ##_SPI_CMD, \
|
|
+ [SPI_INT_STATUS] = SPI_BCM_## __cpu ##_SPI_INT_STATUS, \
|
|
+ [SPI_INT_MASK_ST] = SPI_BCM_## __cpu ##_SPI_INT_MASK_ST, \
|
|
+ [SPI_INT_MASK] = SPI_BCM_## __cpu ##_SPI_INT_MASK, \
|
|
+ [SPI_ST] = SPI_BCM_## __cpu ##_SPI_ST, \
|
|
+ [SPI_CLK_CFG] = SPI_BCM_## __cpu ##_SPI_CLK_CFG, \
|
|
+ [SPI_FILL_BYTE] = SPI_BCM_## __cpu ##_SPI_FILL_BYTE, \
|
|
+ [SPI_MSG_TAIL] = SPI_BCM_## __cpu ##_SPI_MSG_TAIL, \
|
|
+ [SPI_RX_TAIL] = SPI_BCM_## __cpu ##_SPI_RX_TAIL, \
|
|
+ [SPI_MSG_CTL] = SPI_BCM_## __cpu ##_SPI_MSG_CTL, \
|
|
+ [SPI_MSG_DATA] = SPI_BCM_## __cpu ##_SPI_MSG_DATA, \
|
|
+ [SPI_RX_DATA] = SPI_BCM_## __cpu ##_SPI_RX_DATA,
|
|
+
|
|
+static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
|
|
+{
|
|
+#ifdef BCMCPU_RUNTIME_DETECT
|
|
+ extern const unsigned long *bcm63xx_regs_spi;
|
|
+ return bcm63xx_regs_spi[reg];
|
|
+#else
|
|
+#ifdef CONFIG_BCM63XX_CPU_6338
|
|
+ __GEN_SPI_RSET(6338)
|
|
+#endif
|
|
+#ifdef CONFIG_BCM63XX_CPU_6348
|
|
+ __GEN_SPI_RSET(6348)
|
|
+#endif
|
|
+#ifdef CONFIG_BCM63XX_CPU_6358
|
|
+ __GEN_SPI_RSET(6358)
|
|
+#endif
|
|
+#endif
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#endif /* BCM63XX_DEV_SPI_H */
|
|
--- a/arch/mips/bcm63xx/Makefile
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+++ b/arch/mips/bcm63xx/Makefile
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@@ -1,5 +1,5 @@
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obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
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- dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o \
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+ dev-dsp.o dev-enet.o dev-pcmcia.o dev-spi.o dev-uart.o \
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dev-usb-ehci.o dev-usb-ohci.o dev-wdt.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
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+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
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@@ -29,6 +29,7 @@
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#include <bcm63xx_dev_pcmcia.h>
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#include <bcm63xx_dev_usb_ohci.h>
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#include <bcm63xx_dev_usb_ehci.h>
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+#include <bcm63xx_dev_spi.h>
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#include <board_bcm963xx.h>
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#include <bcm_tag.h>
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@@ -972,6 +973,8 @@ int __init board_register_devices(void)
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if (board.num_spis)
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spi_register_board_info(board.spis, board.num_spis);
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+ bcm63xx_spi_register();
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+
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/* read base address of boot chip select (0) */
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val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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val &= MPI_CSBASE_BASE_MASK;
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