mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-12 03:26:15 +02:00
dc3d3f1c49
it's basically also provided by ingenic and nativly based on 2.6.27, adjusted to fit into the OpenWrt-environment
300 lines
5.9 KiB
C
300 lines
5.9 KiB
C
/*
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* linux/arch/mips/jz4750/irq.c
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*
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* JZ4750 interrupt routines.
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*
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* Copyright (c) 2006-2007 Ingenic Semiconductor Inc.
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* Author: <lhhuang@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/delay.h>
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#include <linux/bitops.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/jzsoc.h>
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/*
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* INTC irq type
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*/
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static void enable_intc_irq(unsigned int irq)
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{
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__intc_unmask_irq(irq);
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}
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static void disable_intc_irq(unsigned int irq)
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{
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__intc_mask_irq(irq);
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}
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static void mask_and_ack_intc_irq(unsigned int irq)
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{
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__intc_mask_irq(irq);
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__intc_ack_irq(irq);
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}
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static void end_intc_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
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enable_intc_irq(irq);
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}
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}
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static unsigned int startup_intc_irq(unsigned int irq)
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{
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enable_intc_irq(irq);
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return 0;
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}
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static void shutdown_intc_irq(unsigned int irq)
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{
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disable_intc_irq(irq);
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}
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static struct irq_chip intc_irq_type = {
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.typename = "INTC",
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.startup = startup_intc_irq,
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.shutdown = shutdown_intc_irq,
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.enable = enable_intc_irq,
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.disable = disable_intc_irq,
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.ack = mask_and_ack_intc_irq,
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.end = end_intc_irq,
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};
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/*
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* GPIO irq type
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*/
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static void enable_gpio_irq(unsigned int irq)
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{
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unsigned int intc_irq;
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if (irq < (IRQ_GPIO_0 + 32)) {
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intc_irq = IRQ_GPIO0;
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}
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else if (irq < (IRQ_GPIO_0 + 64)) {
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intc_irq = IRQ_GPIO1;
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}
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else if (irq < (IRQ_GPIO_0 + 96)) {
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intc_irq = IRQ_GPIO2;
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}
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else if (irq < (IRQ_GPIO_0 + 128)) {
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intc_irq = IRQ_GPIO3;
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}
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else if (irq < (IRQ_GPIO_0 + 160)) {
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intc_irq = IRQ_GPIO4;
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}
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else {
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intc_irq = IRQ_GPIO5;
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}
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enable_intc_irq(intc_irq);
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__gpio_unmask_irq(irq - IRQ_GPIO_0);
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}
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static void disable_gpio_irq(unsigned int irq)
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{
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__gpio_mask_irq(irq - IRQ_GPIO_0);
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}
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static void mask_and_ack_gpio_irq(unsigned int irq)
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{
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__gpio_mask_irq(irq - IRQ_GPIO_0);
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__gpio_ack_irq(irq - IRQ_GPIO_0);
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}
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static void end_gpio_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
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enable_gpio_irq(irq);
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}
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}
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static unsigned int startup_gpio_irq(unsigned int irq)
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{
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enable_gpio_irq(irq);
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return 0;
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}
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static void shutdown_gpio_irq(unsigned int irq)
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{
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disable_gpio_irq(irq);
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}
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static struct irq_chip gpio_irq_type = {
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.typename = "GPIO",
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.startup = startup_gpio_irq,
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.shutdown = shutdown_gpio_irq,
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.enable = enable_gpio_irq,
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.disable = disable_gpio_irq,
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.ack = mask_and_ack_gpio_irq,
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.end = end_gpio_irq,
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};
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/*
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* DMA irq type
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*/
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static void enable_dma_irq(unsigned int irq)
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{
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unsigned int intc_irq;
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if ( irq < (IRQ_DMA_0 + HALF_DMA_NUM) ) /* DMAC Group 0 irq */
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intc_irq = IRQ_DMAC0;
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else if ( irq < (IRQ_DMA_0 + MAX_DMA_NUM) ) /* DMAC Group 1 irq */
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intc_irq = IRQ_DMAC1;
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else {
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printk("%s, unexpected dma irq #%d\n", __FILE__, irq);
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return;
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}
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__intc_unmask_irq(intc_irq);
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__dmac_channel_enable_irq(irq - IRQ_DMA_0);
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}
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static void disable_dma_irq(unsigned int irq)
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{
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__dmac_channel_disable_irq(irq - IRQ_DMA_0);
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}
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static void mask_and_ack_dma_irq(unsigned int irq)
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{
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unsigned int intc_irq;
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if ( irq < (IRQ_DMA_0 + HALF_DMA_NUM) ) /* DMAC Group 0 irq */
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intc_irq = IRQ_DMAC0;
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else if ( irq < (IRQ_DMA_0 + MAX_DMA_NUM) ) /* DMAC Group 1 irq */
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intc_irq = IRQ_DMAC1;
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else {
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printk("%s, unexpected dma irq #%d\n", __FILE__, irq);
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return ;
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}
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__intc_ack_irq(intc_irq);
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__dmac_channel_ack_irq(irq-IRQ_DMA_0); /* needed?? add 20080506, Wolfgang */
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__dmac_channel_disable_irq(irq - IRQ_DMA_0);
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}
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static void end_dma_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
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enable_dma_irq(irq);
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}
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}
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static unsigned int startup_dma_irq(unsigned int irq)
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{
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enable_dma_irq(irq);
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return 0;
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}
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static void shutdown_dma_irq(unsigned int irq)
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{
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disable_dma_irq(irq);
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}
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static struct irq_chip dma_irq_type = {
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.typename = "DMA",
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.startup = startup_dma_irq,
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.shutdown = shutdown_dma_irq,
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.enable = enable_dma_irq,
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.disable = disable_dma_irq,
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.ack = mask_and_ack_dma_irq,
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.end = end_dma_irq,
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};
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//----------------------------------------------------------------------
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void __init arch_init_irq(void)
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{
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int i;
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clear_c0_status(0xff04); /* clear ERL */
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set_c0_status(0x0400); /* set IP2 */
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/* Set up INTC irq
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*/
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for (i = 0; i < 32; i++) {
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disable_intc_irq(i);
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irq_desc[i].chip = &intc_irq_type;
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}
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/* Set up DMAC irq
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*/
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for (i = 0; i < NUM_DMA; i++) {
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disable_dma_irq(IRQ_DMA_0 + i);
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irq_desc[IRQ_DMA_0 + i].chip = &dma_irq_type;
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}
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/* Set up GPIO irq
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*/
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for (i = 0; i < NUM_GPIO; i++) {
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disable_gpio_irq(IRQ_GPIO_0 + i);
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irq_desc[IRQ_GPIO_0 + i].chip = &gpio_irq_type;
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}
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}
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static int plat_real_irq(int irq)
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{
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switch (irq) {
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case IRQ_GPIO0:
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irq = __gpio_group_irq(0) + IRQ_GPIO_0;
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break;
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case IRQ_GPIO1:
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irq = __gpio_group_irq(1) + IRQ_GPIO_0 + 32;
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break;
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case IRQ_GPIO2:
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irq = __gpio_group_irq(2) + IRQ_GPIO_0 + 64;
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break;
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case IRQ_GPIO3:
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irq = __gpio_group_irq(3) + IRQ_GPIO_0 + 96;
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break;
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case IRQ_GPIO4:
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irq = __gpio_group_irq(4) + IRQ_GPIO_0 + 128;
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break;
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case IRQ_GPIO5:
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irq = __gpio_group_irq(5) + IRQ_GPIO_0 + 160;
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break;
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case IRQ_DMAC0:
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case IRQ_DMAC1:
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irq = __dmac_get_irq() + IRQ_DMA_0;
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break;
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}
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return irq;
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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int irq = 0;
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static unsigned long intc_ipr = 0;
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intc_ipr |= REG_INTC_IPR;
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if (!intc_ipr) return;
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irq = ffs(intc_ipr) - 1;
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intc_ipr &= ~(1<<irq);
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irq = plat_real_irq(irq);
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do_IRQ(irq);
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}
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