mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-09 21:41:53 +02:00
ca78cbf57d
The defined offset is wrong and the fixup-code overrides it later on so that it never gets used for most PCI devices. Unfortunately the yenta-socket allocates its own resources and crashes because of the wrong mem_offset. It seems that the offset and fixup code came from 2.4 where resource allocation was handled differently. This patch removes the unneeded parts and thus enables the yenta_socket on the WRT54G3G platform. It was tested on Asus WL500G-Premium (v1 and v2), Linksys WRT54G3G, Netgear WGT634U Signed-off-by: Michael Buesch <mb@bu3sch.de> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20239 3c298f89-4303-0410-b956-a3cf2f4a3e73
54 lines
1.8 KiB
Diff
54 lines
1.8 KiB
Diff
Index: linux-2.6.33/drivers/ssb/driver_pcicore.c
|
|
===================================================================
|
|
--- linux-2.6.33.orig/drivers/ssb/driver_pcicore.c 2010-03-15 14:52:55.000000000 +0100
|
|
+++ linux-2.6.33/drivers/ssb/driver_pcicore.c 2010-03-15 15:57:38.000000000 +0100
|
|
@@ -246,20 +246,12 @@
|
|
.pci_ops = &ssb_pcicore_pciops,
|
|
.io_resource = &ssb_pcicore_io_resource,
|
|
.mem_resource = &ssb_pcicore_mem_resource,
|
|
- .mem_offset = 0x24000000,
|
|
};
|
|
|
|
-static u32 ssb_pcicore_pcibus_iobase = 0x100;
|
|
-static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
|
|
-
|
|
/* This function is called when doing a pci_enable_device().
|
|
* We must first check if the device is a device on the PCI-core bridge. */
|
|
int ssb_pcicore_plat_dev_init(struct pci_dev *d)
|
|
{
|
|
- struct resource *res;
|
|
- int pos, size;
|
|
- u32 *base;
|
|
-
|
|
if (d->bus->ops != &ssb_pcicore_pciops) {
|
|
/* This is not a device on the PCI-core bridge. */
|
|
return -ENODEV;
|
|
@@ -268,27 +260,6 @@
|
|
ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
|
|
pci_name(d));
|
|
|
|
- /* Fix up resource bases */
|
|
- for (pos = 0; pos < 6; pos++) {
|
|
- res = &d->resource[pos];
|
|
- if (res->flags & IORESOURCE_IO)
|
|
- base = &ssb_pcicore_pcibus_iobase;
|
|
- else
|
|
- base = &ssb_pcicore_pcibus_membase;
|
|
- res->flags |= IORESOURCE_PCI_FIXED;
|
|
- if (res->end) {
|
|
- size = res->end - res->start + 1;
|
|
- if (*base & (size - 1))
|
|
- *base = (*base + size) & ~(size - 1);
|
|
- res->start = *base;
|
|
- res->end = res->start + size - 1;
|
|
- *base += size;
|
|
- pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
|
|
- }
|
|
- /* Fix up PCI bridge BAR0 only */
|
|
- if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
|
|
- break;
|
|
- }
|
|
/* Fix up interrupt lines */
|
|
d->irq = ssb_mips_irq(extpci_core->dev) + 2;
|
|
pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
|