mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31902 3c298f89-4303-0410-b956-a3cf2f4a3e73
299 lines
8.0 KiB
Diff
299 lines
8.0 KiB
Diff
From d0f0d5739a31c12d349980ed05a670fa1e84696d Mon Sep 17 00:00:00 2001
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From: Maarten ter Huurne <maarten@treewalker.org>
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Date: Wed, 16 Mar 2011 03:16:04 +0100
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Subject: [PATCH 12/21] MIPS: JZ4740: Add cpufreq support.
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This is a squashed version of Uli's driver that was further developed in the opendingux-kernel repository.
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---
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arch/mips/Kconfig | 1 +
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arch/mips/jz4740/Makefile | 1 +
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arch/mips/jz4740/cpufreq.c | 226 ++++++++++++++++++++++++++++++++++++++
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arch/mips/kernel/cpufreq/Kconfig | 13 ++-
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4 files changed, 240 insertions(+), 1 deletions(-)
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create mode 100644 arch/mips/jz4740/cpufreq.c
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -212,6 +212,7 @@ config MACH_JZ4740
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select HAVE_PWM
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select HAVE_CLK
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select GENERIC_IRQ_CHIP
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+ select CPU_SUPPORTS_CPUFREQ
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config LANTIQ
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bool "Lantiq based platforms"
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--- a/arch/mips/jz4740/Makefile
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+++ b/arch/mips/jz4740/Makefile
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@@ -16,5 +16,6 @@ obj-$(CONFIG_JZ4740_QI_LB60) += board-qi
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# PM support
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obj-$(CONFIG_PM) += pm.o
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+obj-$(CONFIG_CPU_FREQ_JZ) += cpufreq.o
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ccflags-y := -Werror -Wall
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--- /dev/null
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+++ b/arch/mips/jz4740/cpufreq.c
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@@ -0,0 +1,226 @@
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+/*
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+ * linux/arch/mips/jz4740/cpufreq.c
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+ *
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+ * cpufreq driver for JZ4740
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+ *
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+ * Copyright (c) 2010 Ulrich Hecht <ulrich.hecht@gmail.com>
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+ * Copyright (c) 2010 Maarten ter Huurne <maarten@treewalker.org>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/init.h>
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+#include <linux/err.h>
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+
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+#include <linux/cpufreq.h>
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+
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+#include <linux/clk.h>
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+#include <asm/mach-jz4740/base.h>
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+
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+#include "clock.h"
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+
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+#define DEBUG_CPUFREQ
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+
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+#ifdef DEBUG_CPUFREQ
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+#define dprintk(X...) printk(KERN_INFO X)
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+#else
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+#define dprintk(X...) do { } while(0)
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+#endif
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+
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+#define HCLK_MIN 30000
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+/* TODO: The maximum MCLK most likely depends on the SDRAM chips used,
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+ so it is board-specific. */
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+#define MCLK_MAX 140000
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+
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+/* Same as jz_clk_main_divs, but with 24 and 32 removed because the hardware
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+ spec states those dividers must not be used for CCLK or HCLK. */
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+static const unsigned int jz4740_freq_cpu_divs[] = {1, 2, 3, 4, 6, 8, 12, 16};
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+
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+struct jz4740_freq_percpu_info {
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+ unsigned int pll_rate;
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+ struct cpufreq_frequency_table table[
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+ ARRAY_SIZE(jz4740_freq_cpu_divs) + 1];
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+};
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+
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+static struct clk *pll;
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+static struct clk *cclk;
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+
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+static struct jz4740_freq_percpu_info jz4740_freq_info;
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+
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+static struct cpufreq_driver cpufreq_jz4740_driver;
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+
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+static void jz4740_freq_fill_table(struct cpufreq_policy *policy,
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+ unsigned int pll_rate)
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+{
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+ struct cpufreq_frequency_table *table = &jz4740_freq_info.table[0];
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+ int i;
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+
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+#ifdef CONFIG_CPU_FREQ_STAT_DETAILS
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+ /* for showing /sys/devices/system/cpu/cpuX/cpufreq/stats/ */
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+ static bool init = false;
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+ if (init)
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+ cpufreq_frequency_table_put_attr(policy->cpu);
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+ else
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+ init = true;
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+#endif
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+
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+ jz4740_freq_info.pll_rate = pll_rate;
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+
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+ for (i = 0; i < ARRAY_SIZE(jz4740_freq_cpu_divs); i++) {
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+ unsigned int freq = pll_rate / jz4740_freq_cpu_divs[i];
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+ if (freq < HCLK_MIN) break;
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+ table[i].index = i;
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+ table[i].frequency = freq;
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+ }
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+ table[i].index = i;
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+ table[i].frequency = CPUFREQ_TABLE_END;
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+
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+ policy->min = table[i - 1].frequency;
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+ policy->max = table[0].frequency;
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+
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+#ifdef CONFIG_CPU_FREQ_STAT_DETAILS
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+ cpufreq_frequency_table_get_attr(table, policy->cpu);
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+#endif
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+}
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+
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+static unsigned int jz4740_freq_get(unsigned int cpu)
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+{
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+ return clk_get_rate(cclk) / 1000;
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+}
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+
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+static int jz4740_freq_verify(struct cpufreq_policy *policy)
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+{
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+ unsigned int new_pll;
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+
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+ cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
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+ policy->cpuinfo.max_freq);
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+
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+ new_pll = clk_round_rate(pll, policy->max * 1000) / 1000;
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+ if (jz4740_freq_info.pll_rate != new_pll)
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+ jz4740_freq_fill_table(policy, new_pll);
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+
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+ return 0;
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+}
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+
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+static int jz4740_freq_target(struct cpufreq_policy *policy,
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+ unsigned int target_freq,
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+ unsigned int relation)
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+{
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+ struct cpufreq_frequency_table *table = &jz4740_freq_info.table[0];
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+ struct cpufreq_freqs freqs;
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+ unsigned int new_index = 0;
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+ unsigned int old_pll = clk_get_rate(pll) / 1000;
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+ unsigned int new_pll = jz4740_freq_info.pll_rate;
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+ int ret = 0;
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+
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+ if (cpufreq_frequency_table_target(policy, table,
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+ target_freq, relation, &new_index))
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+ return -EINVAL;
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+ freqs = (struct cpufreq_freqs) {
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+ .old = jz4740_freq_get(policy->cpu),
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+ .new = table[new_index].frequency,
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+ .cpu = policy->cpu,
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+ .flags = cpufreq_jz4740_driver.flags,
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+ };
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+ if (freqs.new != freqs.old || new_pll != old_pll) {
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+ unsigned int cdiv, hdiv, mdiv, pdiv;
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+ cdiv = jz4740_freq_cpu_divs[new_index];
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+ hdiv = (cdiv == 3 || cdiv == 6) ? cdiv * 2 : cdiv * 3;
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+ while (new_pll < HCLK_MIN * hdiv)
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+ hdiv -= cdiv;
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+ mdiv = hdiv;
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+ if (new_pll > MCLK_MAX * mdiv) {
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+ /* 4,4 performs better than 3,6 */
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+ if (new_pll > MCLK_MAX * 4)
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+ mdiv *= 2;
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+ else
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+ hdiv = mdiv = cdiv * 4;
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+ }
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+ pdiv = mdiv;
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+ dprintk(KERN_INFO "%s: cclk %p, setting from %d to %d, "
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+ "dividers %d, %d, %d, %d\n",
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+ __FUNCTION__, cclk, freqs.old, freqs.new,
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+ cdiv, hdiv, mdiv, pdiv);
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+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
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+ ret = clk_main_set_dividers(new_pll == old_pll,
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+ cdiv, hdiv, mdiv, pdiv);
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+ if (ret) {
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+ dprintk(KERN_INFO "failed to set dividers\n");
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+ } else if (new_pll != old_pll) {
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+ dprintk(KERN_INFO "%s: pll %p, setting from %d to %d\n",
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+ __FUNCTION__, pll, old_pll, new_pll);
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+ ret = clk_set_rate(pll, new_pll * 1000);
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+ }
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+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
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+ }
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+
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+ return ret;
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+}
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+
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+static int jz4740_cpufreq_driver_init(struct cpufreq_policy *policy)
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+{
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+ int ret;
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+
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+ dprintk(KERN_INFO "Jz4740 cpufreq driver\n");
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+
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+ if (policy->cpu != 0)
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+ return -EINVAL;
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+
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+ pll = clk_get(NULL, "pll");
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+ if (IS_ERR(pll)) {
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+ ret = PTR_ERR(pll);
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+ goto err_exit;
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+ }
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+
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+ cclk = clk_get(NULL, "cclk");
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+ if (IS_ERR(cclk)) {
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+ ret = PTR_ERR(cclk);
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+ goto err_clk_put_pll;
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+ }
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+
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+ policy->cpuinfo.min_freq = HCLK_MIN;
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+ policy->cpuinfo.max_freq = 500000;
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+ policy->cpuinfo.transition_latency = 100000; /* in nanoseconds */
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+ policy->cur = jz4740_freq_get(policy->cpu);
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+ policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
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+ /* min and max are set by jz4740_freq_fill_table() */
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+
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+ jz4740_freq_fill_table(policy, clk_get_rate(pll) / 1000 /* in kHz */);
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+
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+ return 0;
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+
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+err_clk_put_pll:
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+ clk_put(pll);
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+err_exit:
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+ return ret;
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+}
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+
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+static struct cpufreq_driver cpufreq_jz4740_driver = {
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+ .init = jz4740_cpufreq_driver_init,
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+ .verify = jz4740_freq_verify,
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+ .target = jz4740_freq_target,
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+ .get = jz4740_freq_get,
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+ .name = "jz4740",
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+};
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+
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+static int __init jz4740_cpufreq_init(void)
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+{
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+ return cpufreq_register_driver(&cpufreq_jz4740_driver);
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+}
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+
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+static void __exit jz4740_cpufreq_exit(void)
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+{
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+ cpufreq_unregister_driver(&cpufreq_jz4740_driver);
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+}
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+
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+module_init(jz4740_cpufreq_init);
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+module_exit(jz4740_cpufreq_exit);
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+
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+MODULE_AUTHOR("Ulrich Hecht <ulrich.hecht@gmail.com>, "
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+ "Maarten ter Huurne <maarten@treewalker.org>");
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+MODULE_DESCRIPTION("cpufreq driver for Jz4740");
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+MODULE_LICENSE("GPL");
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--- a/arch/mips/kernel/cpufreq/Kconfig
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+++ b/arch/mips/kernel/cpufreq/Kconfig
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@@ -8,7 +8,7 @@ config MIPS_EXTERNAL_TIMER
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config MIPS_CPUFREQ
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bool
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default y
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- depends on CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
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+ depends on CPU_SUPPORTS_CPUFREQ
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if MIPS_CPUFREQ
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@@ -24,6 +24,7 @@ config LOONGSON2_CPUFREQ
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tristate "Loongson2 CPUFreq Driver"
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select CPU_FREQ_TABLE
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depends on MIPS_CPUFREQ
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+ depends on MIPS_EXTERNAL_TIMER
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help
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This option adds a CPUFreq driver for loongson processors which
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support software configurable cpu frequency.
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@@ -34,6 +35,16 @@ config LOONGSON2_CPUFREQ
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If in doubt, say N.
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+config CPU_FREQ_JZ
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+ tristate "CPUfreq driver for JZ CPUs"
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+ select CPU_FREQ_TABLE
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+ depends on MACH_JZ4740
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+ default n
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+ help
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+ This enables the CPUfreq driver for JZ CPUs.
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+
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+ If in doubt, say N.
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+
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endif # CPU_FREQ
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endmenu
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