mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-13 05:31:10 +03:00
656f01b9c9
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20789 3c298f89-4303-0410-b956-a3cf2f4a3e73
36 lines
1.1 KiB
Diff
36 lines
1.1 KiB
Diff
Index: linux-2.6.32.10/arch/mips/kernel/cevt-r4k.c
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===================================================================
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--- linux-2.6.32.10.orig/arch/mips/kernel/cevt-r4k.c 2010-04-02 21:11:39.000000000 +0200
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+++ linux-2.6.32.10/arch/mips/kernel/cevt-r4k.c 2010-04-02 21:11:52.000000000 +0200
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@@ -22,6 +22,22 @@
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#ifndef CONFIG_MIPS_MT_SMTC
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+/*
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+ * Compare interrupt can be routed and latched outside the core,
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+ * so a single execution hazard barrier may not be enough to give
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+ * it time to clear as seen in the Cause register. 4 time the
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+ * pipeline depth seems reasonably conservative, and empirically
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+ * works better in configurations with high CPU/bus clock ratios.
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+ */
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+
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+#define compare_change_hazard() \
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+ do { \
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+ irq_disable_hazard(); \
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+ irq_disable_hazard(); \
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+ irq_disable_hazard(); \
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+ irq_disable_hazard(); \
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+ } while (0)
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+
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static int mips_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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@@ -31,6 +47,7 @@
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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+ compare_change_hazard();
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res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
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return res;
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}
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