mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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1a29ef8e97
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19815 3c298f89-4303-0410-b956-a3cf2f4a3e73
314 lines
9.2 KiB
C
314 lines
9.2 KiB
C
/*
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* plio.h
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* PLIO defines.
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*
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* Copyright © 2009 Ubicom Inc. <www.ubicom.com>. All Rights Reserved.
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*
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* This file is part of the Ubicom32 Linux Kernel Port.
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*
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* The Ubicom32 Linux Kernel Port is free software: you can
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* redistribute it and/or modify it under the terms of the GNU General
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* Public License as published by the Free Software Foundation, either
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* version 2 of the License, or (at your option) any later version.
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*
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* The Ubicom32 Linux Kernel Port is distributed in the hope that it
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* will be useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with the Ubicom32 Linux Kernel Port. If not,
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* see <http://www.gnu.org/licenses/>.
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* This file contains confidential information of Ubicom, Inc. and your use of
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* this file is subject to the Ubicom Software License Agreement distributed with
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* this file. If you are uncertain whether you are an authorized user or to report
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* any unauthorized use, please contact Ubicom, Inc. at +1-408-789-2200.
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* Unauthorized reproduction or distribution of this file is subject to civil and
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* criminal penalties.
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*/
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#ifndef __PLIO__H__
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#define __PLIO__H__
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#include <asm/ip5000.h>
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#include <asm/thread.h>
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#define PLIO_PORT RD
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#define PLIO_EXT_PORT RI
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#define TRANSMIT_FIFO_WATERMARK 8
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/*
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* PLIO non-blocking register definitions
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*/
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#define PLIO_FN 2
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typedef struct {
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unsigned : 10;
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unsigned rxfifo_thread_enable: 1; /* allowed rxfifo thread enable */
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unsigned : 1;
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unsigned rxfifo_thread: 4; /* allowed rxfifo thread access */
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unsigned : 4;
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unsigned br_thread: 4; /* allowed blocking region thread access */
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unsigned fn_reset: 4; /* function reset bit vector */
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unsigned rxfifo_sel: 1; /* select between RXFIFO 0 and 1 */
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unsigned fn_sel: 3; /* select port function */
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} plio_io_function_t;
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typedef struct {
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unsigned : 24;
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unsigned pin:8;
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} plio_gpio_t;
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typedef struct {
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unsigned : 16;
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unsigned txfifo_uf: 1; /* TXFIFO underflow */
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unsigned txfifo_wm: 1; /* TXFIFO watermark */
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unsigned rxfifo_of: 1; /* RXFIFO overflow */
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unsigned rxfifo_wm: 1; /* RXFIFO watermark */
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unsigned : 5;
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unsigned lreg_int_addr_rd: 1; /* read from specified LREG address */
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unsigned lreg_int_addr_wr: 1; /* write to specified LREG address */
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unsigned extctl_int: 4; /* synchronized external interrupts */
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unsigned pfsm_int: 1; /* state machine */
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} plio_intstat_t;
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typedef struct {
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unsigned txfifo_reset: 1; /* TXFIFO reset for int_set only */
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unsigned rxfifo_reset: 1; /* RXFIFO reset for int_set only */
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unsigned : 11;
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unsigned idif_txfifo_flush: 1; /* flush TXFIFO and idif_txfifo */
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unsigned idif_rxfifo_flush: 1; /* flush RXFIFO and idif_rxfifo */
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unsigned pfsm_start: 1; /* input to fsm */
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unsigned txfifo_uf: 1; /* TXFIFO underflow */
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unsigned txfifo_wm: 1; /* TXFIFO watermark */
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unsigned rxfifo_of: 1; /* RXFIFO overflow */
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unsigned rxfifo_wm: 1; /* RXFIFO watermark */
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unsigned : 5;
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unsigned lreg_int_addr_rd: 1; /* read from specified LREG address */
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unsigned lreg_int_addr_wr: 1; /* write to specified LREG address */
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unsigned extctl_int: 4; /* synchronized external interrupts */
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unsigned pfsm_int: 1; /* state machine */
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} plio_intset_t;
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typedef enum {
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PLIO_PORT_MODE_D,
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PLIO_PORT_MODE_DE,
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PLIO_PORT_MODE_DI,
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PLIO_PORT_MODE_DEI,
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PLIO_PORT_MODE_DC,
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} plio_port_mode_t;
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typedef enum {
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PLIO_CLK_CORE, /* CORE CLK */
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PLIO_CLK_IO, /* IO CLK */
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PLIO_CLK_EXT, /* EXT CLK */
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} plio_clk_src_t;
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typedef struct {
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unsigned : 4;
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unsigned edif_iaena_sel: 1; /* Input Address Enable Select */
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unsigned edif_iaclk_sel: 1; /* Input Address Clock Select */
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unsigned edif_iald_inv: 1; /* Input Address Strobe Invert */
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unsigned edif_idclk_sel: 1; /* Input Data Clock Select */
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unsigned edif_idld_inv: 1; /* Input Data Strobe Invert */
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unsigned edif_ds: 3; /* specify IDR and ODR data shift */
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unsigned edif_cmp_mode: 1; /* configure IDR comparator output */
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unsigned edif_idena_sel: 1; /* Input Data Enable Select */
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unsigned ecif_extclk_ena: 1; /* plio_extctl output select */
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unsigned idif_tx_fifo_cmd_sel: 1; /* select pfsm_cmd data word position */
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unsigned ptif_porti_cfg: 2; /* select port I pin configuration */
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unsigned ptif_portd_cfg: 3; /* select port D pin configuration */
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plio_port_mode_t ptif_port_mode: 3; /* select other plio ports */
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unsigned icif_clk_plio_ext_inv: 1; /* invert external plio clock when set */
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unsigned icif_rst_plio: 1; /* reset plio function and io fifos */
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plio_clk_src_t icif_clk_src_sel: 2; /* select plio clock source */
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unsigned pfsm_prog: 1; /* enable pfsm programming */
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unsigned pfsm_cmd: 3; /* software input to pfsm */
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} plio_fctl0_t;
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typedef struct {
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unsigned : 2;
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unsigned idif_byteswap_tx: 3; /* swap TXFIFO byte order */
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unsigned idif_byteswap_rx: 3; /* swap RXFIFO byte order */
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unsigned : 1;
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unsigned lreg_ena: 1; /* enable local register map */
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unsigned lreg_addr_fifo_cmp_ena: 1; /* enable a specific LREG address from/to TX/RX fifos */
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unsigned lreg_addr_fifo_cmp: 5; /* LREG address routed from/to TX/RX fifos */
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unsigned : 1;
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unsigned dcod_iald_idld_sel: 2; /* select address/data strobes */
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unsigned dcod_rw_src_sel: 1; /* select LREG strobe source */
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unsigned dcod_rd_sel: 5; /* select read strobe source */
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unsigned dcod_wr_sel: 5; /* select write strobe source */
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unsigned dcod_rd_lvl: 1; /* select active level of read strobe */
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unsigned dcod_wr_lvl: 1; /* select active level of read strobe */
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} plio_fctl1_t;
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typedef struct {
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unsigned icif_eclk_div: 16; /* external plio clock divider */
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unsigned icif_iclk_div: 16; /* internal plio clock divider */
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} plio_fctl2_t;
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typedef struct {
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unsigned : 27;
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unsigned pfsm_state: 5; /* current pfsm state */
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} plio_stat_0_t;
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typedef struct {
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unsigned : 3;
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unsigned lreg_r_int_addr: 5;
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unsigned : 11;
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unsigned lreg_w_int_addr: 5;
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unsigned lreg_w_int_data: 8;
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} plio_stat_1_t;
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typedef struct {
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unsigned : 32;
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} plio_stat_2_t;
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typedef struct {
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unsigned tx: 16;
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unsigned rx: 16;
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} plio_io_fifo_wm_t, plio_io_fifo_lvl_t;
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/* plio blocking region register definitions
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*/
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typedef struct {
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unsigned ns1: 5;
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unsigned ic1: 7;
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unsigned ec1: 4;
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unsigned ns0: 5;
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unsigned ic0: 7;
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unsigned ec0: 4;
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} plio_sram_t;
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typedef struct {
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unsigned : 2;
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unsigned s9: 3;
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unsigned s8: 3;
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unsigned s7: 3;
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unsigned s6: 3;
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unsigned s5: 3;
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unsigned s4: 3;
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unsigned s3: 3;
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unsigned s2: 3;
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unsigned s1: 3;
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unsigned s0: 3;
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} plio_grpsel_t;
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typedef struct {
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unsigned s7: 4;
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unsigned s6: 4;
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unsigned s5: 4;
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unsigned s4: 4;
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unsigned s3: 4;
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unsigned s2: 4;
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unsigned s1: 4;
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unsigned s0: 4;
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} plio_cs_lut_t;
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typedef struct {
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unsigned lut3: 8;
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unsigned lut2: 8;
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unsigned lut1: 8;
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unsigned lut0: 8;
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} plio_extctl_t;
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typedef struct {
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plio_grpsel_t grpsel[4];
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u16_t cv[16];
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plio_cs_lut_t cs_lut[4];
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plio_extctl_t extctl_o_lut[8];
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} plio_pfsm_t;
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typedef struct {
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u32_t odr_oe_sel;
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u32_t odr_oe;
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u32_t cmp;
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u32_t ncmp;
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u32_t cmp_mask;
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} plio_edif_t;
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typedef enum {
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PLIO_ECIF_CLK_OUT = 9,
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PLIO_ECIF_IALD = 9,
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PLIO_ECIF_CLK_IN = 8,
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PLIO_ECIF_IDLD = 8,
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PLIO_ECIF_INT = 2,
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} plio_ecif_output_t;
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typedef struct {
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u32_t bypass_sync;
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u32_t ift;
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u32_t output_type;
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u32_t output_ena;
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u32_t output_lvl;
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} plio_ecif_t;
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typedef struct {
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u32_t idr_addr_pos_mask;
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u32_t reserved;
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u32_t lreg_bar;
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} plio_dcod_t;
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typedef struct {
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u32_t addr_rd_ena;
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u32_t addr_wr_ena;
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u32_t addr_rd_int_ena;
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u32_t addr_wr_int_ena;
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} plio_lcfg_t;
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/*
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* PLIO configuration
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*/
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typedef struct {
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plio_fctl0_t fctl0;
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plio_fctl1_t fctl1;
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plio_fctl2_t fctl2;
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} plio_fctl_t;
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typedef struct {
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plio_pfsm_t pfsm;
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plio_edif_t edif;
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plio_ecif_t ecif;
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plio_dcod_t dcod;
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plio_lcfg_t lcfg;
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} plio_config_t;
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typedef struct {
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plio_io_function_t function;
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plio_gpio_t gpio_ctl;
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plio_gpio_t gpio_out;
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plio_gpio_t gpio_in;
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plio_intstat_t intstat;
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plio_intstat_t intmask;
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plio_intset_t intset;
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plio_intstat_t intclr;
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unsigned tx_lo;
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unsigned tx_hi;
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unsigned rx_lo;
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unsigned rx_hi;
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plio_fctl0_t fctl0;
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plio_fctl1_t fctl1;
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plio_fctl2_t fctl2;
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plio_stat_0_t stat0;
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plio_stat_1_t stat1;
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plio_stat_2_t stat2;
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plio_io_fifo_wm_t fifo_wm;
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plio_io_fifo_lvl_t fifo_lvl;
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} plio_nbr_t;
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typedef struct {
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u32_t pfsm_sram[256];
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plio_config_t config;
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} plio_br_t;
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#define PLIO_NBR ((plio_nbr_t *)(PLIO_PORT))
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#define PLIO_BR ((plio_br_t *)((PLIO_PORT + IO_PORT_BR_OFFSET)))
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#define PEXT_NBR ((plio_nbr_t *)(PLIO_EXT_PORT))
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extern void plio_init(const plio_fctl_t *plio_fctl, const plio_config_t *plio_config, const plio_sram_t plio_sram_cfg[], int sram_cfg_size);
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#endif // __PLIO__H__
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