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df88996997
The nand subtarget is not working yet. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33983 3c298f89-4303-0410-b956-a3cf2f4a3e73
168 lines
6.0 KiB
Diff
168 lines
6.0 KiB
Diff
From f465a16766a015a31d4e83af1ad62cc718d64f5a Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Sun, 24 Jun 2012 13:43:08 +0200
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Subject: [PATCH 18/34] MIPS: ath79: add clock setup for the QCA955X SoCs
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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arch/mips/ath79/clock.c | 78 ++++++++++++++++++++++++
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 39 ++++++++++++
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2 files changed, 117 insertions(+), 0 deletions(-)
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo
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iounmap(dpll_base);
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}
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+static void __init qca955x_clocks_init(void)
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+{
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+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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+ u32 cpu_pll, ddr_pll;
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+ u32 bootstrap;
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+
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+ bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
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+ if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
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+ ath79_ref_clk.rate = 40 * 1000 * 1000;
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+ else
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+ ath79_ref_clk.rate = 25 * 1000 * 1000;
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+
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+ pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
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+ out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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+ QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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+ QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
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+ nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
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+ QCA955X_PLL_CPU_CONFIG_NINT_MASK;
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+ frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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+ QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
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+
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+ cpu_pll = nint * ath79_ref_clk.rate / ref_div;
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+ cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
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+ cpu_pll /= (1 << out_div);
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+
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+ pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
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+ out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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+ QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
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+ ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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+ QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
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+ nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
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+ QCA955X_PLL_DDR_CONFIG_NINT_MASK;
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+ frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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+ QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
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+
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+ ddr_pll = nint * ath79_ref_clk.rate / ref_div;
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+ ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
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+ ddr_pll /= (1 << out_div);
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+
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+ clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
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+
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+ postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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+ QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
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+ ath79_cpu_clk.rate = ath79_ref_clk.rate;
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+ else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
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+ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
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+ else
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+ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
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+
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+ postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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+ QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
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+ ath79_ddr_clk.rate = ath79_ref_clk.rate;
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+ else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
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+ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
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+ else
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+ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
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+
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+ postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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+ QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
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+
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+ if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
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+ ath79_ahb_clk.rate = ath79_ref_clk.rate;
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+ else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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+ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
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+ else
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+ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
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+
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+ ath79_wdt_clk.rate = ath79_ref_clk.rate;
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+ ath79_uart_clk.rate = ath79_ref_clk.rate;
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+}
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+
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void __init ath79_clocks_init(void)
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{
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if (soc_is_ar71xx())
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@@ -307,6 +383,8 @@ void __init ath79_clocks_init(void)
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ar933x_clocks_init();
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else if (soc_is_ar934x())
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ar934x_clocks_init();
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+ else if (soc_is_qca955x())
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+ qca955x_clocks_init();
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else
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BUG();
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -225,6 +225,41 @@
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
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#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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+#define QCA955X_PLL_CPU_CONFIG_REG 0x00
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+#define QCA955X_PLL_DDR_CONFIG_REG 0x04
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+#define QCA955X_PLL_CLK_CTRL_REG 0x08
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+
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+#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
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+#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
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+#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6
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+#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f
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+#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
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+#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
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+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
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+#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
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+
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+#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
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+#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
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+#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10
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+#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f
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+#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
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+#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
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+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
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+#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
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+
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+#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
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+#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
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+#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
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+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
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+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
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+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
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+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
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+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
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+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
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+#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
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+#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
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+#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
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+
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/*
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* USB_CONFIG block
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*/
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@@ -264,6 +299,8 @@
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#define AR934X_RESET_REG_BOOTSTRAP 0xb0
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#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
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+#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
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+
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#define MISC_INT_ETHSW BIT(12)
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#define MISC_INT_TIMER4 BIT(10)
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#define MISC_INT_TIMER3 BIT(9)
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@@ -341,6 +378,8 @@
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#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
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#define AR934X_BOOTSTRAP_DDR1 BIT(0)
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+#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
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+
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#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
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#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
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#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
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