mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-20 22:59:18 +03:00
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34042 3c298f89-4303-0410-b956-a3cf2f4a3e73
1025 lines
31 KiB
Diff
1025 lines
31 KiB
Diff
--- a/drivers/bcma/Kconfig
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+++ b/drivers/bcma/Kconfig
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@@ -48,12 +48,12 @@ config BCMA_DRIVER_MIPS
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config BCMA_SFLASH
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bool
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- depends on BCMA_DRIVER_MIPS && BROKEN
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+ depends on BCMA_DRIVER_MIPS
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default y
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config BCMA_NFLASH
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bool
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- depends on BCMA_DRIVER_MIPS && BROKEN
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+ depends on BCMA_DRIVER_MIPS
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default y
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config BCMA_DRIVER_GMAC_CMN
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--- a/drivers/bcma/bcma_private.h
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+++ b/drivers/bcma/bcma_private.h
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@@ -54,6 +54,7 @@ u32 bcma_pmu_get_clockcpu(struct bcma_dr
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#ifdef CONFIG_BCMA_SFLASH
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/* driver_chipcommon_sflash.c */
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int bcma_sflash_init(struct bcma_drv_cc *cc);
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+extern struct platform_device bcma_sflash_dev;
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#else
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static inline int bcma_sflash_init(struct bcma_drv_cc *cc)
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{
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@@ -65,6 +66,7 @@ static inline int bcma_sflash_init(struc
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#ifdef CONFIG_BCMA_NFLASH
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/* driver_chipcommon_nflash.c */
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int bcma_nflash_init(struct bcma_drv_cc *cc);
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+extern struct platform_device bcma_nflash_dev;
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#else
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static inline int bcma_nflash_init(struct bcma_drv_cc *cc)
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{
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--- a/drivers/bcma/core.c
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+++ b/drivers/bcma/core.c
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@@ -65,7 +65,7 @@ void bcma_core_set_clockmode(struct bcma
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switch (clkmode) {
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case BCMA_CLKMODE_FAST:
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bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
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- udelay(64);
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+ usleep_range(64, 300);
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for (i = 0; i < 1500; i++) {
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if (bcma_read32(core, BCMA_CLKCTLST) &
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BCMA_CLKCTLST_HAVEHT) {
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--- a/drivers/bcma/driver_chipcommon.c
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+++ b/drivers/bcma/driver_chipcommon.c
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@@ -22,12 +22,9 @@ static inline u32 bcma_cc_write32_masked
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return value;
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}
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-void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
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+void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
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{
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- u32 leddc_on = 10;
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- u32 leddc_off = 90;
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-
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- if (cc->setup_done)
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+ if (cc->early_setup_done)
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return;
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if (cc->core->id.rev >= 11)
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@@ -36,6 +33,22 @@ void bcma_core_chipcommon_init(struct bc
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if (cc->core->id.rev >= 35)
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cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
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+ if (cc->capabilities & BCMA_CC_CAP_PMU)
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+ bcma_pmu_early_init(cc);
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+
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+ cc->early_setup_done = true;
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+}
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+
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+void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
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+{
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+ u32 leddc_on = 10;
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+ u32 leddc_off = 90;
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+
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+ if (cc->setup_done)
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+ return;
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+
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+ bcma_core_chipcommon_early_init(cc);
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+
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if (cc->core->id.rev >= 20) {
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bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
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bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
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--- a/drivers/bcma/driver_chipcommon_nflash.c
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+++ b/drivers/bcma/driver_chipcommon_nflash.c
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@@ -5,15 +5,40 @@
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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+#include <linux/platform_device.h>
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#include <linux/bcma/bcma.h>
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-#include <linux/bcma/bcma_driver_chipcommon.h>
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-#include <linux/delay.h>
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#include "bcma_private.h"
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+struct platform_device bcma_nflash_dev = {
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+ .name = "bcma_nflash",
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+ .num_resources = 0,
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+};
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+
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/* Initialize NAND flash access */
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int bcma_nflash_init(struct bcma_drv_cc *cc)
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{
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- bcma_err(cc->core->bus, "NAND flash support is broken\n");
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+ struct bcma_bus *bus = cc->core->bus;
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+
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+ if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
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+ cc->core->id.rev != 0x38) {
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+ bcma_err(bus, "NAND flash on unsupported board!\n");
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+ return -ENOTSUPP;
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+ }
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+
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+ if (!(cc->capabilities & BCMA_CC_CAP_NFLASH)) {
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+ bcma_err(bus, "NAND flash not present according to ChipCommon\n");
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+ return -ENODEV;
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+ }
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+
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+ cc->nflash.present = true;
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+ if (cc->core->id.rev == 38 &&
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+ (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
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+ cc->nflash.boot = true;
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+
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+ /* Prepare platform device, but don't register it yet. It's too early,
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+ * malloc (required by device_private_init) is not available yet. */
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+ bcma_nflash_dev.dev.platform_data = &cc->nflash;
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+
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return 0;
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}
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--- a/drivers/bcma/driver_chipcommon_pmu.c
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+++ b/drivers/bcma/driver_chipcommon_pmu.c
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@@ -76,7 +76,10 @@ static void bcma_pmu_resources_init(stru
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if (max_msk)
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bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
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- /* Add some delay; allow resources to come up and settle. */
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+ /*
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+ * Add some delay; allow resources to come up and settle.
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+ * Delay is required for SoC (early init).
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+ */
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mdelay(2);
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}
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@@ -101,7 +104,7 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
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bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
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}
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-void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
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+static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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@@ -141,7 +144,7 @@ void bcma_pmu_workarounds(struct bcma_dr
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}
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}
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-void bcma_pmu_init(struct bcma_drv_cc *cc)
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+void bcma_pmu_early_init(struct bcma_drv_cc *cc)
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{
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u32 pmucap;
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@@ -150,7 +153,10 @@ void bcma_pmu_init(struct bcma_drv_cc *c
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bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
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cc->pmu.rev, pmucap);
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+}
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+void bcma_pmu_init(struct bcma_drv_cc *cc)
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+{
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if (cc->pmu.rev == 1)
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bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
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~BCMA_CC_PMU_CTL_NOILPONW);
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@@ -257,7 +263,7 @@ static u32 bcma_pmu_clock_bcm4706(struct
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}
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/* query bus clock frequency for PMU-enabled chipcommon */
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-u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
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+static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
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{
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struct bcma_bus *bus = cc->core->bus;
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--- a/drivers/bcma/driver_chipcommon_sflash.c
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+++ b/drivers/bcma/driver_chipcommon_sflash.c
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@@ -5,15 +5,161 @@
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* Licensed under the GNU/GPL. See COPYING for details.
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*/
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+#include <linux/platform_device.h>
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#include <linux/bcma/bcma.h>
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-#include <linux/bcma/bcma_driver_chipcommon.h>
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-#include <linux/delay.h>
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#include "bcma_private.h"
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+static struct resource bcma_sflash_resource = {
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+ .name = "bcma_sflash",
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+ .start = BCMA_SOC_FLASH2,
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+ .end = 0,
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+ .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
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+};
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+
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+struct platform_device bcma_sflash_dev = {
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+ .name = "bcma_sflash",
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+ .resource = &bcma_sflash_resource,
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+ .num_resources = 1,
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+};
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+
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+struct bcma_sflash_tbl_e {
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+ char *name;
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+ u32 id;
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+ u32 blocksize;
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+ u16 numblocks;
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+};
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+
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+static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
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+ { "M25P20", 0x11, 0x10000, 4, },
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+ { "M25P40", 0x12, 0x10000, 8, },
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+
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+ { "M25P16", 0x14, 0x10000, 32, },
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+ { "M25P32", 0x14, 0x10000, 64, },
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+ { "M25P64", 0x16, 0x10000, 128, },
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+ { "M25FL128", 0x17, 0x10000, 256, },
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+ { 0 },
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+};
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+
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+static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
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+ { "SST25WF512", 1, 0x1000, 16, },
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+ { "SST25VF512", 0x48, 0x1000, 16, },
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+ { "SST25WF010", 2, 0x1000, 32, },
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+ { "SST25VF010", 0x49, 0x1000, 32, },
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+ { "SST25WF020", 3, 0x1000, 64, },
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+ { "SST25VF020", 0x43, 0x1000, 64, },
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+ { "SST25WF040", 4, 0x1000, 128, },
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+ { "SST25VF040", 0x44, 0x1000, 128, },
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+ { "SST25VF040B", 0x8d, 0x1000, 128, },
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+ { "SST25WF080", 5, 0x1000, 256, },
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+ { "SST25VF080B", 0x8e, 0x1000, 256, },
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+ { "SST25VF016", 0x41, 0x1000, 512, },
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+ { "SST25VF032", 0x4a, 0x1000, 1024, },
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+ { "SST25VF064", 0x4b, 0x1000, 2048, },
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+ { 0 },
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+};
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+
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+static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
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+ { "AT45DB011", 0xc, 256, 512, },
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+ { "AT45DB021", 0x14, 256, 1024, },
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+ { "AT45DB041", 0x1c, 256, 2048, },
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+ { "AT45DB081", 0x24, 256, 4096, },
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+ { "AT45DB161", 0x2c, 512, 4096, },
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+ { "AT45DB321", 0x34, 512, 8192, },
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+ { "AT45DB642", 0x3c, 1024, 8192, },
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+ { 0 },
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+};
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+
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+static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
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+{
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+ int i;
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+ bcma_cc_write32(cc, BCMA_CC_FLASHCTL,
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+ BCMA_CC_FLASHCTL_START | opcode);
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+ for (i = 0; i < 1000; i++) {
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+ if (!(bcma_cc_read32(cc, BCMA_CC_FLASHCTL) &
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+ BCMA_CC_FLASHCTL_BUSY))
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+ return;
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+ cpu_relax();
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+ }
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+ bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
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+}
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+
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/* Initialize serial flash access */
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int bcma_sflash_init(struct bcma_drv_cc *cc)
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{
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- bcma_err(cc->core->bus, "Serial flash support is broken\n");
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+ struct bcma_bus *bus = cc->core->bus;
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+ struct bcma_sflash *sflash = &cc->sflash;
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+ struct bcma_sflash_tbl_e *e;
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+ u32 id, id2;
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+
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+ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
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+ case BCMA_CC_FLASHT_STSER:
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_DP);
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+
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+ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 0);
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
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+ id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
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+
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+ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 1);
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
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+ id2 = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
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+
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+ switch (id) {
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+ case 0xbf:
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+ for (e = bcma_sflash_sst_tbl; e->name; e++) {
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+ if (e->id == id2)
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+ break;
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+ }
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+ break;
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+ case 0x13:
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+ return -ENOTSUPP;
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+ default:
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+ for (e = bcma_sflash_st_tbl; e->name; e++) {
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+ if (e->id == id)
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+ break;
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+ }
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+ break;
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+ }
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+ if (!e->name) {
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+ bcma_err(bus, "Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n", id, id2);
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+ return -ENOTSUPP;
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+ }
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+
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+ break;
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+ case BCMA_CC_FLASHT_ATSER:
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS);
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+ id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA) & 0x3c;
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+
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+ for (e = bcma_sflash_at_tbl; e->name; e++) {
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+ if (e->id == id)
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+ break;
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+ }
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+ if (!e->name) {
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+ bcma_err(bus, "Unsupported Atmel serial flash (id: 0x%X)\n", id);
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+ return -ENOTSUPP;
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+ }
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+
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+ break;
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+ default:
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+ bcma_err(bus, "Unsupported flash type\n");
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+ return -ENOTSUPP;
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+ }
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+
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+ sflash->window = BCMA_SOC_FLASH2;
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+ sflash->blocksize = e->blocksize;
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+ sflash->numblocks = e->numblocks;
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+ sflash->size = sflash->blocksize * sflash->numblocks;
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+ sflash->present = true;
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+
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+ bcma_info(bus, "Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
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+ e->name, sflash->size / 1024, sflash->blocksize,
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+ sflash->numblocks);
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+
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+ /* Prepare platform device, but don't register it yet. It's too early,
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+ * malloc (required by device_private_init) is not available yet. */
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+ bcma_sflash_dev.resource[0].end = bcma_sflash_dev.resource[0].start +
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+ sflash->size;
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+ bcma_sflash_dev.dev.platform_data = sflash;
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+
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return 0;
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}
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--- a/drivers/bcma/driver_mips.c
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+++ b/drivers/bcma/driver_mips.c
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@@ -181,47 +181,66 @@ EXPORT_SYMBOL(bcma_cpu_clock);
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static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
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{
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struct bcma_bus *bus = mcore->core->bus;
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+ struct bcma_drv_cc *cc = &bus->drv_cc;
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- switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
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+ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
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case BCMA_CC_FLASHT_STSER:
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case BCMA_CC_FLASHT_ATSER:
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bcma_debug(bus, "Found serial flash\n");
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- bcma_sflash_init(&bus->drv_cc);
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+ bcma_sflash_init(cc);
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break;
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case BCMA_CC_FLASHT_PARA:
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bcma_debug(bus, "Found parallel flash\n");
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- bus->drv_cc.pflash.window = 0x1c000000;
|
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- bus->drv_cc.pflash.window_size = 0x02000000;
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+ cc->pflash.present = true;
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+ cc->pflash.window = BCMA_SOC_FLASH2;
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+ cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
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|
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- if ((bcma_read32(bus->drv_cc.core, BCMA_CC_FLASH_CFG) &
|
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+ if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
|
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BCMA_CC_FLASH_CFG_DS) == 0)
|
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- bus->drv_cc.pflash.buswidth = 1;
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+ cc->pflash.buswidth = 1;
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else
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- bus->drv_cc.pflash.buswidth = 2;
|
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+ cc->pflash.buswidth = 2;
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break;
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default:
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bcma_err(bus, "Flash type not supported\n");
|
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}
|
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|
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- if (bus->drv_cc.core->id.rev == 38 ||
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+ if (cc->core->id.rev == 38 ||
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bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
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- if (bus->drv_cc.capabilities & BCMA_CC_CAP_NFLASH) {
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+ if (cc->capabilities & BCMA_CC_CAP_NFLASH) {
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bcma_debug(bus, "Found NAND flash\n");
|
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- bcma_nflash_init(&bus->drv_cc);
|
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+ bcma_nflash_init(cc);
|
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}
|
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}
|
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}
|
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|
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+void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
|
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+{
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+ struct bcma_bus *bus = mcore->core->bus;
|
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+
|
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+ if (mcore->early_setup_done)
|
|
+ return;
|
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+
|
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+ bcma_chipco_serial_init(&bus->drv_cc);
|
|
+ bcma_core_mips_flash_detect(mcore);
|
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+
|
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+ mcore->early_setup_done = true;
|
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+}
|
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+
|
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void bcma_core_mips_init(struct bcma_drv_mips *mcore)
|
|
{
|
|
struct bcma_bus *bus;
|
|
struct bcma_device *core;
|
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bus = mcore->core->bus;
|
|
|
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+ if (mcore->setup_done)
|
|
+ return;
|
|
+
|
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bcma_info(bus, "Initializing MIPS core...\n");
|
|
|
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- if (!mcore->setup_done)
|
|
- mcore->assigned_irqs = 1;
|
|
+ bcma_core_mips_early_init(mcore);
|
|
+
|
|
+ mcore->assigned_irqs = 1;
|
|
|
|
/* Assign IRQs to all cores on the bus */
|
|
list_for_each_entry(core, &bus->cores, list) {
|
|
@@ -256,10 +275,5 @@ void bcma_core_mips_init(struct bcma_drv
|
|
bcma_info(bus, "IRQ reconfiguration done\n");
|
|
bcma_core_mips_dump_irq(bus);
|
|
|
|
- if (mcore->setup_done)
|
|
- return;
|
|
-
|
|
- bcma_chipco_serial_init(&bus->drv_cc);
|
|
- bcma_core_mips_flash_detect(mcore);
|
|
mcore->setup_done = true;
|
|
}
|
|
--- a/drivers/bcma/driver_pci.c
|
|
+++ b/drivers/bcma/driver_pci.c
|
|
@@ -51,7 +51,7 @@ static void bcma_pcie_mdio_set_phy(struc
|
|
v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
|
|
if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
|
|
break;
|
|
- msleep(1);
|
|
+ usleep_range(1000, 2000);
|
|
}
|
|
}
|
|
|
|
@@ -92,7 +92,7 @@ static u16 bcma_pcie_mdio_read(struct bc
|
|
ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA);
|
|
break;
|
|
}
|
|
- msleep(1);
|
|
+ usleep_range(1000, 2000);
|
|
}
|
|
pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
|
|
return ret;
|
|
@@ -132,7 +132,7 @@ static void bcma_pcie_mdio_write(struct
|
|
v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL);
|
|
if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE)
|
|
break;
|
|
- msleep(1);
|
|
+ usleep_range(1000, 2000);
|
|
}
|
|
pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
|
|
}
|
|
--- a/drivers/bcma/driver_pci_host.c
|
|
+++ b/drivers/bcma/driver_pci_host.c
|
|
@@ -35,11 +35,6 @@ bool __devinit bcma_core_pci_is_in_hostm
|
|
chipid_top != 0x5300)
|
|
return false;
|
|
|
|
- if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
|
|
- bcma_info(bus, "This PCI core is disabled and not working\n");
|
|
- return false;
|
|
- }
|
|
-
|
|
bcma_core_enable(pc->core, 0);
|
|
|
|
return !mips_busprobe32(tmp, pc->core->io_addr);
|
|
@@ -396,6 +391,11 @@ void __devinit bcma_core_pci_hostmode_in
|
|
|
|
bcma_info(bus, "PCIEcore in host mode found\n");
|
|
|
|
+ if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
|
|
+ bcma_info(bus, "This PCIE core is disabled and not working\n");
|
|
+ return;
|
|
+ }
|
|
+
|
|
pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
|
|
if (!pc_host) {
|
|
bcma_err(bus, "can not allocate memory");
|
|
@@ -425,9 +425,9 @@ void __devinit bcma_core_pci_hostmode_in
|
|
pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
|
|
|
|
/* Reset RC */
|
|
- udelay(3000);
|
|
+ usleep_range(3000, 5000);
|
|
pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
|
|
- udelay(1000);
|
|
+ usleep_range(1000, 2000);
|
|
pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
|
|
BCMA_CORE_PCI_CTL_RST_OE);
|
|
|
|
@@ -452,6 +452,8 @@ void __devinit bcma_core_pci_hostmode_in
|
|
pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
|
|
pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
|
|
BCMA_SOC_PCI_MEM_SZ - 1;
|
|
+ pc_host->io_resource.start = 0x100;
|
|
+ pc_host->io_resource.end = 0x47F;
|
|
pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
|
|
pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
|
|
tmp | BCMA_SOC_PCI_MEM);
|
|
@@ -459,6 +461,8 @@ void __devinit bcma_core_pci_hostmode_in
|
|
pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
|
|
pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
|
|
BCMA_SOC_PCI_MEM_SZ - 1;
|
|
+ pc_host->io_resource.start = 0x480;
|
|
+ pc_host->io_resource.end = 0x7FF;
|
|
pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
|
|
pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
|
|
pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
|
|
@@ -481,7 +485,7 @@ void __devinit bcma_core_pci_hostmode_in
|
|
* before issuing configuration requests to PCI Express
|
|
* devices.
|
|
*/
|
|
- udelay(100000);
|
|
+ msleep(100);
|
|
|
|
bcma_core_pci_enable_crs(pc);
|
|
|
|
@@ -501,7 +505,7 @@ void __devinit bcma_core_pci_hostmode_in
|
|
set_io_port_base(pc_host->pci_controller.io_map_base);
|
|
/* Give some time to the PCI controller to configure itself with the new
|
|
* values. Not waiting at this point causes crashes of the machine. */
|
|
- mdelay(10);
|
|
+ usleep_range(10000, 15000);
|
|
register_pci_controller(&pc_host->pci_controller);
|
|
return;
|
|
}
|
|
--- a/drivers/bcma/host_pci.c
|
|
+++ b/drivers/bcma/host_pci.c
|
|
@@ -77,8 +77,8 @@ static void bcma_host_pci_write32(struct
|
|
}
|
|
|
|
#ifdef CONFIG_BCMA_BLOCKIO
|
|
-void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
|
|
- size_t count, u16 offset, u8 reg_width)
|
|
+static void bcma_host_pci_block_read(struct bcma_device *core, void *buffer,
|
|
+ size_t count, u16 offset, u8 reg_width)
|
|
{
|
|
void __iomem *addr = core->bus->mmio + offset;
|
|
if (core->bus->mapped_core != core)
|
|
@@ -100,8 +100,9 @@ void bcma_host_pci_block_read(struct bcm
|
|
}
|
|
}
|
|
|
|
-void bcma_host_pci_block_write(struct bcma_device *core, const void *buffer,
|
|
- size_t count, u16 offset, u8 reg_width)
|
|
+static void bcma_host_pci_block_write(struct bcma_device *core,
|
|
+ const void *buffer, size_t count,
|
|
+ u16 offset, u8 reg_width)
|
|
{
|
|
void __iomem *addr = core->bus->mmio + offset;
|
|
if (core->bus->mapped_core != core)
|
|
@@ -139,7 +140,7 @@ static void bcma_host_pci_awrite32(struc
|
|
iowrite32(value, core->bus->mmio + (1 * BCMA_CORE_SIZE) + offset);
|
|
}
|
|
|
|
-const struct bcma_host_ops bcma_host_pci_ops = {
|
|
+static const struct bcma_host_ops bcma_host_pci_ops = {
|
|
.read8 = bcma_host_pci_read8,
|
|
.read16 = bcma_host_pci_read16,
|
|
.read32 = bcma_host_pci_read32,
|
|
@@ -272,6 +273,7 @@ static DEFINE_PCI_DEVICE_TABLE(bcma_pci_
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
|
|
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
|
|
{ 0, },
|
|
--- a/drivers/bcma/host_soc.c
|
|
+++ b/drivers/bcma/host_soc.c
|
|
@@ -143,7 +143,7 @@ static void bcma_host_soc_awrite32(struc
|
|
writel(value, core->io_wrap + offset);
|
|
}
|
|
|
|
-const struct bcma_host_ops bcma_host_soc_ops = {
|
|
+static const struct bcma_host_ops bcma_host_soc_ops = {
|
|
.read8 = bcma_host_soc_read8,
|
|
.read16 = bcma_host_soc_read16,
|
|
.read32 = bcma_host_soc_read32,
|
|
--- a/drivers/bcma/main.c
|
|
+++ b/drivers/bcma/main.c
|
|
@@ -7,6 +7,7 @@
|
|
|
|
#include "bcma_private.h"
|
|
#include <linux/module.h>
|
|
+#include <linux/platform_device.h>
|
|
#include <linux/bcma/bcma.h>
|
|
#include <linux/slab.h>
|
|
|
|
@@ -80,6 +81,18 @@ struct bcma_device *bcma_find_core(struc
|
|
}
|
|
EXPORT_SYMBOL_GPL(bcma_find_core);
|
|
|
|
+static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
|
|
+ u8 unit)
|
|
+{
|
|
+ struct bcma_device *core;
|
|
+
|
|
+ list_for_each_entry(core, &bus->cores, list) {
|
|
+ if (core->id.id == coreid && core->core_unit == unit)
|
|
+ return core;
|
|
+ }
|
|
+ return NULL;
|
|
+}
|
|
+
|
|
static void bcma_release_core_dev(struct device *dev)
|
|
{
|
|
struct bcma_device *core = container_of(dev, struct bcma_device, dev);
|
|
@@ -136,6 +149,22 @@ static int bcma_register_cores(struct bc
|
|
dev_id++;
|
|
}
|
|
|
|
+#ifdef CONFIG_BCMA_SFLASH
|
|
+ if (bus->drv_cc.sflash.present) {
|
|
+ err = platform_device_register(&bcma_sflash_dev);
|
|
+ if (err)
|
|
+ bcma_err(bus, "Error registering serial flash\n");
|
|
+ }
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_BCMA_NFLASH
|
|
+ if (bus->drv_cc.nflash.present) {
|
|
+ err = platform_device_register(&bcma_nflash_dev);
|
|
+ if (err)
|
|
+ bcma_err(bus, "Error registering NAND flash\n");
|
|
+ }
|
|
+#endif
|
|
+
|
|
return 0;
|
|
}
|
|
|
|
@@ -166,6 +195,20 @@ int __devinit bcma_bus_register(struct b
|
|
return -1;
|
|
}
|
|
|
|
+ /* Early init CC core */
|
|
+ core = bcma_find_core(bus, bcma_cc_core_id(bus));
|
|
+ if (core) {
|
|
+ bus->drv_cc.core = core;
|
|
+ bcma_core_chipcommon_early_init(&bus->drv_cc);
|
|
+ }
|
|
+
|
|
+ /* Try to get SPROM */
|
|
+ err = bcma_sprom_get(bus);
|
|
+ if (err == -ENOENT) {
|
|
+ bcma_err(bus, "No SPROM available\n");
|
|
+ } else if (err)
|
|
+ bcma_err(bus, "Failed to get SPROM: %d\n", err);
|
|
+
|
|
/* Init CC core */
|
|
core = bcma_find_core(bus, bcma_cc_core_id(bus));
|
|
if (core) {
|
|
@@ -181,10 +224,17 @@ int __devinit bcma_bus_register(struct b
|
|
}
|
|
|
|
/* Init PCIE core */
|
|
- core = bcma_find_core(bus, BCMA_CORE_PCIE);
|
|
+ core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 0);
|
|
+ if (core) {
|
|
+ bus->drv_pci[0].core = core;
|
|
+ bcma_core_pci_init(&bus->drv_pci[0]);
|
|
+ }
|
|
+
|
|
+ /* Init PCIE core */
|
|
+ core = bcma_find_core_unit(bus, BCMA_CORE_PCIE, 1);
|
|
if (core) {
|
|
- bus->drv_pci.core = core;
|
|
- bcma_core_pci_init(&bus->drv_pci);
|
|
+ bus->drv_pci[1].core = core;
|
|
+ bcma_core_pci_init(&bus->drv_pci[1]);
|
|
}
|
|
|
|
/* Init GBIT MAC COMMON core */
|
|
@@ -194,13 +244,6 @@ int __devinit bcma_bus_register(struct b
|
|
bcma_core_gmac_cmn_init(&bus->drv_gmac_cmn);
|
|
}
|
|
|
|
- /* Try to get SPROM */
|
|
- err = bcma_sprom_get(bus);
|
|
- if (err == -ENOENT) {
|
|
- bcma_err(bus, "No SPROM available\n");
|
|
- } else if (err)
|
|
- bcma_err(bus, "Failed to get SPROM: %d\n", err);
|
|
-
|
|
/* Register found cores */
|
|
bcma_register_cores(bus);
|
|
|
|
@@ -211,7 +254,17 @@ int __devinit bcma_bus_register(struct b
|
|
|
|
void bcma_bus_unregister(struct bcma_bus *bus)
|
|
{
|
|
+ struct bcma_device *cores[3];
|
|
+
|
|
+ cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
|
|
+ cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
|
|
+ cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
|
|
+
|
|
bcma_unregister_cores(bus);
|
|
+
|
|
+ kfree(cores[2]);
|
|
+ kfree(cores[1]);
|
|
+ kfree(cores[0]);
|
|
}
|
|
|
|
int __init bcma_bus_early_register(struct bcma_bus *bus,
|
|
@@ -248,18 +301,18 @@ int __init bcma_bus_early_register(struc
|
|
return -1;
|
|
}
|
|
|
|
- /* Init CC core */
|
|
+ /* Early init CC core */
|
|
core = bcma_find_core(bus, bcma_cc_core_id(bus));
|
|
if (core) {
|
|
bus->drv_cc.core = core;
|
|
- bcma_core_chipcommon_init(&bus->drv_cc);
|
|
+ bcma_core_chipcommon_early_init(&bus->drv_cc);
|
|
}
|
|
|
|
- /* Init MIPS core */
|
|
+ /* Early init MIPS core */
|
|
core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
|
|
if (core) {
|
|
bus->drv_mips.core = core;
|
|
- bcma_core_mips_init(&bus->drv_mips);
|
|
+ bcma_core_mips_early_init(&bus->drv_mips);
|
|
}
|
|
|
|
bcma_info(bus, "Early bus registered\n");
|
|
--- a/drivers/bcma/sprom.c
|
|
+++ b/drivers/bcma/sprom.c
|
|
@@ -507,7 +507,9 @@ static bool bcma_sprom_onchip_available(
|
|
/* for these chips OTP is always available */
|
|
present = true;
|
|
break;
|
|
+ case BCMA_CHIP_ID_BCM43227:
|
|
case BCMA_CHIP_ID_BCM43228:
|
|
+ case BCMA_CHIP_ID_BCM43428:
|
|
present = chip_status & BCMA_CC_CHIPST_43228_OTP_PRESENT;
|
|
break;
|
|
default:
|
|
@@ -593,8 +595,11 @@ int bcma_sprom_get(struct bcma_bus *bus)
|
|
bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
|
|
|
|
err = bcma_sprom_valid(sprom);
|
|
- if (err)
|
|
+ if (err) {
|
|
+ bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
|
|
+ err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
|
|
goto out;
|
|
+ }
|
|
|
|
bcma_sprom_extract_r8(bus, sprom);
|
|
|
|
--- a/include/linux/bcma/bcma.h
|
|
+++ b/include/linux/bcma/bcma.h
|
|
@@ -10,7 +10,7 @@
|
|
#include <linux/bcma/bcma_driver_gmac_cmn.h>
|
|
#include <linux/ssb/ssb.h> /* SPROM sharing */
|
|
|
|
-#include "bcma_regs.h"
|
|
+#include <linux/bcma/bcma_regs.h>
|
|
|
|
struct bcma_device;
|
|
struct bcma_bus;
|
|
@@ -251,7 +251,7 @@ struct bcma_bus {
|
|
u8 num;
|
|
|
|
struct bcma_drv_cc drv_cc;
|
|
- struct bcma_drv_pci drv_pci;
|
|
+ struct bcma_drv_pci drv_pci[2];
|
|
struct bcma_drv_mips drv_mips;
|
|
struct bcma_drv_gmac_cmn drv_gmac_cmn;
|
|
|
|
--- a/include/linux/bcma/bcma_driver_chipcommon.h
|
|
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
|
|
@@ -100,6 +100,7 @@
|
|
#define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
|
|
#define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
|
|
#define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
|
|
+#define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
|
|
#define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
|
|
#define BCMA_CC_JCMD_START 0x80000000
|
|
#define BCMA_CC_JCMD_BUSY 0x80000000
|
|
@@ -266,6 +267,29 @@
|
|
#define BCMA_CC_SROM_CONTROL_SIZE_16K 0x00000004
|
|
#define BCMA_CC_SROM_CONTROL_SIZE_SHIFT 1
|
|
#define BCMA_CC_SROM_CONTROL_PRESENT 0x00000001
|
|
+/* Block 0x140 - 0x190 registers are chipset specific */
|
|
+#define BCMA_CC_4706_FLASHSCFG 0x18C /* Flash struct configuration */
|
|
+#define BCMA_CC_4706_FLASHSCFG_MASK 0x000000ff
|
|
+#define BCMA_CC_4706_FLASHSCFG_SF1 0x00000001 /* 2nd serial flash present */
|
|
+#define BCMA_CC_4706_FLASHSCFG_PF1 0x00000002 /* 2nd parallel flash present */
|
|
+#define BCMA_CC_4706_FLASHSCFG_SF1_TYPE 0x00000004 /* 2nd serial flash type : 0 : ST, 1 : Atmel */
|
|
+#define BCMA_CC_4706_FLASHSCFG_NF1 0x00000008 /* 2nd NAND flash present */
|
|
+#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_MASK 0x000000f0
|
|
+#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_4MB 0x00000010 /* 4MB */
|
|
+#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_8MB 0x00000020 /* 8MB */
|
|
+#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_16MB 0x00000030 /* 16MB */
|
|
+#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_32MB 0x00000040 /* 32MB */
|
|
+#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_64MB 0x00000050 /* 64MB */
|
|
+#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_128MB 0x00000060 /* 128MB */
|
|
+#define BCMA_CC_4706_FLASHSCFG_1ST_MADDR_SEG_256MB 0x00000070 /* 256MB */
|
|
+/* NAND flash registers for BCM4706 (corerev = 31) */
|
|
+#define BCMA_CC_NFLASH_CTL 0x01A0
|
|
+#define BCMA_CC_NFLASH_CTL_ERR 0x08000000
|
|
+#define BCMA_CC_NFLASH_CONF 0x01A4
|
|
+#define BCMA_CC_NFLASH_COL_ADDR 0x01A8
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+#define BCMA_CC_NFLASH_ROW_ADDR 0x01AC
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+#define BCMA_CC_NFLASH_DATA 0x01B0
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+#define BCMA_CC_NFLASH_WAITCNT0 0x01B4
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/* 0x1E0 is defined as shared BCMA_CLKCTLST */
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#define BCMA_CC_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
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#define BCMA_CC_UART0_DATA 0x0300
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@@ -325,6 +349,60 @@
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#define BCMA_CC_PLLCTL_ADDR 0x0660
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#define BCMA_CC_PLLCTL_DATA 0x0664
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#define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
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+/* NAND flash MLC controller registers (corerev >= 38) */
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+#define BCMA_CC_NAND_REVISION 0x0C00
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+#define BCMA_CC_NAND_CMD_START 0x0C04
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+#define BCMA_CC_NAND_CMD_ADDR_X 0x0C08
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+#define BCMA_CC_NAND_CMD_ADDR 0x0C0C
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+#define BCMA_CC_NAND_CMD_END_ADDR 0x0C10
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+#define BCMA_CC_NAND_CS_NAND_SELECT 0x0C14
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+#define BCMA_CC_NAND_CS_NAND_XOR 0x0C18
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+#define BCMA_CC_NAND_SPARE_RD0 0x0C20
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+#define BCMA_CC_NAND_SPARE_RD4 0x0C24
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+#define BCMA_CC_NAND_SPARE_RD8 0x0C28
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+#define BCMA_CC_NAND_SPARE_RD12 0x0C2C
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+#define BCMA_CC_NAND_SPARE_WR0 0x0C30
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+#define BCMA_CC_NAND_SPARE_WR4 0x0C34
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+#define BCMA_CC_NAND_SPARE_WR8 0x0C38
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+#define BCMA_CC_NAND_SPARE_WR12 0x0C3C
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+#define BCMA_CC_NAND_ACC_CONTROL 0x0C40
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+#define BCMA_CC_NAND_CONFIG 0x0C48
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+#define BCMA_CC_NAND_TIMING_1 0x0C50
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+#define BCMA_CC_NAND_TIMING_2 0x0C54
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+#define BCMA_CC_NAND_SEMAPHORE 0x0C58
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+#define BCMA_CC_NAND_DEVID 0x0C60
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+#define BCMA_CC_NAND_DEVID_X 0x0C64
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+#define BCMA_CC_NAND_BLOCK_LOCK_STATUS 0x0C68
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+#define BCMA_CC_NAND_INTFC_STATUS 0x0C6C
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+#define BCMA_CC_NAND_ECC_CORR_ADDR_X 0x0C70
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+#define BCMA_CC_NAND_ECC_CORR_ADDR 0x0C74
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+#define BCMA_CC_NAND_ECC_UNC_ADDR_X 0x0C78
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+#define BCMA_CC_NAND_ECC_UNC_ADDR 0x0C7C
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+#define BCMA_CC_NAND_READ_ERROR_COUNT 0x0C80
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+#define BCMA_CC_NAND_CORR_STAT_THRESHOLD 0x0C84
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+#define BCMA_CC_NAND_READ_ADDR_X 0x0C90
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+#define BCMA_CC_NAND_READ_ADDR 0x0C94
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+#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR_X 0x0C98
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+#define BCMA_CC_NAND_PAGE_PROGRAM_ADDR 0x0C9C
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+#define BCMA_CC_NAND_COPY_BACK_ADDR_X 0x0CA0
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+#define BCMA_CC_NAND_COPY_BACK_ADDR 0x0CA4
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+#define BCMA_CC_NAND_BLOCK_ERASE_ADDR_X 0x0CA8
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+#define BCMA_CC_NAND_BLOCK_ERASE_ADDR 0x0CAC
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+#define BCMA_CC_NAND_INV_READ_ADDR_X 0x0CB0
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+#define BCMA_CC_NAND_INV_READ_ADDR 0x0CB4
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+#define BCMA_CC_NAND_BLK_WR_PROTECT 0x0CC0
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+#define BCMA_CC_NAND_ACC_CONTROL_CS1 0x0CD0
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+#define BCMA_CC_NAND_CONFIG_CS1 0x0CD4
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+#define BCMA_CC_NAND_TIMING_1_CS1 0x0CD8
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+#define BCMA_CC_NAND_TIMING_2_CS1 0x0CDC
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+#define BCMA_CC_NAND_SPARE_RD16 0x0D30
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+#define BCMA_CC_NAND_SPARE_RD20 0x0D34
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+#define BCMA_CC_NAND_SPARE_RD24 0x0D38
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+#define BCMA_CC_NAND_SPARE_RD28 0x0D3C
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+#define BCMA_CC_NAND_CACHE_ADDR 0x0D40
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+#define BCMA_CC_NAND_CACHE_DATA 0x0D44
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+#define BCMA_CC_NAND_CTRL_CONFIG 0x0D48
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+#define BCMA_CC_NAND_CTRL_STATUS 0x0D4C
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|
|
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/* Divider allocation in 4716/47162/5356 */
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#define BCMA_CC_PMU5_MAINPLL_CPU 1
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@@ -415,6 +493,13 @@
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/* 4313 Chip specific ChipControl register bits */
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#define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
|
|
|
|
+/* BCM5357 ChipControl register bits */
|
|
+#define BCMA_CHIPCTL_5357_EXTPA BIT(14)
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+#define BCMA_CHIPCTL_5357_ANT_MUX_2O3 BIT(15)
|
|
+#define BCMA_CHIPCTL_5357_NFLASH BIT(16)
|
|
+#define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
|
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+#define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
|
|
+
|
|
/* Data for the PMU, if available.
|
|
* Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
|
|
*/
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|
@@ -425,11 +510,35 @@ struct bcma_chipcommon_pmu {
|
|
|
|
#ifdef CONFIG_BCMA_DRIVER_MIPS
|
|
struct bcma_pflash {
|
|
+ bool present;
|
|
u8 buswidth;
|
|
u32 window;
|
|
u32 window_size;
|
|
};
|
|
|
|
+#ifdef CONFIG_BCMA_SFLASH
|
|
+struct bcma_sflash {
|
|
+ bool present;
|
|
+ u32 window;
|
|
+ u32 blocksize;
|
|
+ u16 numblocks;
|
|
+ u32 size;
|
|
+
|
|
+ struct mtd_info *mtd;
|
|
+};
|
|
+#endif
|
|
+
|
|
+#ifdef CONFIG_BCMA_NFLASH
|
|
+struct mtd_info;
|
|
+
|
|
+struct bcma_nflash {
|
|
+ bool present;
|
|
+ bool boot; /* This is the flash the SoC boots from */
|
|
+
|
|
+ struct mtd_info *mtd;
|
|
+};
|
|
+#endif
|
|
+
|
|
struct bcma_serial_port {
|
|
void *regs;
|
|
unsigned long clockspeed;
|
|
@@ -445,11 +554,18 @@ struct bcma_drv_cc {
|
|
u32 capabilities;
|
|
u32 capabilities_ext;
|
|
u8 setup_done:1;
|
|
+ u8 early_setup_done:1;
|
|
/* Fast Powerup Delay constant */
|
|
u16 fast_pwrup_delay;
|
|
struct bcma_chipcommon_pmu pmu;
|
|
#ifdef CONFIG_BCMA_DRIVER_MIPS
|
|
struct bcma_pflash pflash;
|
|
+#ifdef CONFIG_BCMA_SFLASH
|
|
+ struct bcma_sflash sflash;
|
|
+#endif
|
|
+#ifdef CONFIG_BCMA_NFLASH
|
|
+ struct bcma_nflash nflash;
|
|
+#endif
|
|
|
|
int nr_serial_ports;
|
|
struct bcma_serial_port serial_ports[4];
|
|
@@ -470,6 +586,7 @@ struct bcma_drv_cc {
|
|
bcma_cc_write32(cc, offset, (bcma_cc_read32(cc, offset) & (mask)) | (set))
|
|
|
|
extern void bcma_core_chipcommon_init(struct bcma_drv_cc *cc);
|
|
+extern void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc);
|
|
|
|
extern void bcma_chipco_suspend(struct bcma_drv_cc *cc);
|
|
extern void bcma_chipco_resume(struct bcma_drv_cc *cc);
|
|
@@ -493,6 +610,7 @@ u32 bcma_chipco_gpio_polarity(struct bcm
|
|
|
|
/* PMU support */
|
|
extern void bcma_pmu_init(struct bcma_drv_cc *cc);
|
|
+extern void bcma_pmu_early_init(struct bcma_drv_cc *cc);
|
|
|
|
extern void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset,
|
|
u32 value);
|
|
--- a/include/linux/bcma/bcma_driver_mips.h
|
|
+++ b/include/linux/bcma/bcma_driver_mips.h
|
|
@@ -35,13 +35,16 @@ struct bcma_device;
|
|
struct bcma_drv_mips {
|
|
struct bcma_device *core;
|
|
u8 setup_done:1;
|
|
+ u8 early_setup_done:1;
|
|
unsigned int assigned_irqs;
|
|
};
|
|
|
|
#ifdef CONFIG_BCMA_DRIVER_MIPS
|
|
extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
|
|
+extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
|
|
#else
|
|
static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
|
|
+static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
|
|
#endif
|
|
|
|
extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
|
|
--- a/include/linux/bcma/bcma_regs.h
|
|
+++ b/include/linux/bcma/bcma_regs.h
|
|
@@ -11,11 +11,13 @@
|
|
#define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
|
|
#define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
|
|
#define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
|
|
+#define BCMA_CLKCTLST_EXTRESREQ_SHIFT 8
|
|
#define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
|
|
#define BCMA_CLKCTLST_HAVEHT 0x00020000 /* HT available */
|
|
#define BCMA_CLKCTLST_BP_ON_ALP 0x00040000 /* RO: running on ALP clock */
|
|
#define BCMA_CLKCTLST_BP_ON_HT 0x00080000 /* RO: running on HT clock */
|
|
#define BCMA_CLKCTLST_EXTRESST 0x07000000 /* Mask of external resource status */
|
|
+#define BCMA_CLKCTLST_EXTRESST_SHIFT 24
|
|
/* Is there any BCM4328 on BCMA bus? */
|
|
#define BCMA_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
|
|
#define BCMA_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
|
|
@@ -83,4 +85,9 @@
|
|
* (2 ZettaBytes), high 32 bits
|
|
*/
|
|
|
|
+#define BCMA_SOC_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
|
|
+#define BCMA_SOC_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
|
|
+#define BCMA_SOC_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
|
|
+#define BCMA_SOC_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
|
|
+
|
|
#endif /* LINUX_BCMA_REGS_H_ */
|