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603 lines
15 KiB
C
603 lines
15 KiB
C
/*
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* linux/arch/mips/jz4740/cpufreq.c
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*
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* cpufreq driver for JZ4740
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*
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* Copyright (c) 2006-2007 Ingenic Semiconductor Inc.
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* Author: <lhhuang@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <asm/jzsoc.h>
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#include <asm/processor.h>
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#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
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"cpufreq-jz4740", msg)
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#undef CHANGE_PLL
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#define PLL_UNCHANGED 0
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#define PLL_GOES_UP 1
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#define PLL_GOES_DOWN 2
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#define PLL_WAIT_500NS (500*(__cpm_get_cclk()/1000000000))
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/* Saved the boot-time parameters */
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static struct {
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/* SDRAM parameters */
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unsigned int mclk; /* memory clock, KHz */
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unsigned int tras; /* RAS pulse width, cycles of mclk */
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unsigned int rcd; /* RAS to CAS Delay, cycles of mclk */
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unsigned int tpc; /* RAS Precharge time, cycles of mclk */
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unsigned int trwl; /* Write Precharge Time, cycles of mclk */
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unsigned int trc; /* RAS Cycle Time, cycles of mclk */
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unsigned int rtcor; /* Refresh Time Constant */
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unsigned int sdram_initialized;
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/* LCD parameters */
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unsigned int lcd_clk; /* LCD clock, Hz */
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unsigned int lcdpix_clk; /* LCD Pixel clock, Hz */
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unsigned int lcd_clks_initialized;
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} boot_config;
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struct jz4740_freq_percpu_info {
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struct cpufreq_frequency_table table[7];
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};
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static struct jz4740_freq_percpu_info jz4740_freq_table;
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/*
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* This contains the registers value for an operating point.
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* If only part of a register needs to change then there is
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* a mask value for that register.
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* When going to a new operating point the current register
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* value is ANDed with the ~mask and ORed with the new value.
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*/
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struct dpm_regs {
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u32 cpccr; /* Clock Freq Control Register */
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u32 cpccr_mask; /* Clock Freq Control Register mask */
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u32 cppcr; /* PLL1 Control Register */
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u32 cppcr_mask; /* PLL1 Control Register mask */
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u32 pll_up_flag; /* New PLL freq is higher than current or not */
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};
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extern jz_clocks_t jz_clocks;
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static void jz_update_clocks(void)
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{
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/* Next clocks must be updated if we have changed
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* the PLL or divisors.
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*/
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jz_clocks.cclk = __cpm_get_cclk();
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jz_clocks.hclk = __cpm_get_hclk();
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jz_clocks.mclk = __cpm_get_mclk();
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jz_clocks.pclk = __cpm_get_pclk();
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jz_clocks.lcdclk = __cpm_get_lcdclk();
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jz_clocks.pixclk = __cpm_get_pixclk();
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jz_clocks.i2sclk = __cpm_get_i2sclk();
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jz_clocks.usbclk = __cpm_get_usbclk();
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jz_clocks.mscclk = __cpm_get_mscclk();
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}
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static void
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jz_init_boot_config(void)
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{
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if (!boot_config.lcd_clks_initialized) {
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/* the first time to scale pll */
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boot_config.lcd_clk = __cpm_get_lcdclk();
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boot_config.lcdpix_clk = __cpm_get_pixclk();
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boot_config.lcd_clks_initialized = 1;
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}
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if (!boot_config.sdram_initialized) {
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/* the first time to scale frequencies */
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unsigned int dmcr, rtcor;
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unsigned int tras, rcd, tpc, trwl, trc;
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dmcr = REG_EMC_DMCR;
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rtcor = REG_EMC_RTCOR;
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tras = (dmcr >> 13) & 0x7;
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rcd = (dmcr >> 11) & 0x3;
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tpc = (dmcr >> 8) & 0x7;
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trwl = (dmcr >> 5) & 0x3;
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trc = (dmcr >> 2) & 0x7;
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boot_config.mclk = __cpm_get_mclk() / 1000;
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boot_config.tras = tras + 4;
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boot_config.rcd = rcd + 1;
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boot_config.tpc = tpc + 1;
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boot_config.trwl = trwl + 1;
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boot_config.trc = trc * 2 + 1;
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boot_config.rtcor = rtcor;
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boot_config.sdram_initialized = 1;
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}
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}
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static void jz_update_dram_rtcor(unsigned int new_mclk)
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{
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unsigned int rtcor;
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new_mclk /= 1000;
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rtcor = boot_config.rtcor * new_mclk / boot_config.mclk;
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rtcor--;
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if (rtcor < 1) rtcor = 1;
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if (rtcor > 255) rtcor = 255;
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REG_EMC_RTCOR = rtcor;
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REG_EMC_RTCNT = rtcor;
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}
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static void jz_update_dram_dmcr(unsigned int new_mclk)
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{
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unsigned int dmcr;
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unsigned int tras, rcd, tpc, trwl, trc;
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unsigned int valid_time, new_time; /* ns */
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new_mclk /= 1000;
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tras = boot_config.tras * new_mclk / boot_config.mclk;
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rcd = boot_config.rcd * new_mclk / boot_config.mclk;
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tpc = boot_config.tpc * new_mclk / boot_config.mclk;
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trwl = boot_config.trwl * new_mclk / boot_config.mclk;
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trc = boot_config.trc * new_mclk / boot_config.mclk;
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/* Validation checking */
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valid_time = (boot_config.tras * 1000000) / boot_config.mclk;
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new_time = (tras * 1000000) / new_mclk;
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if (new_time < valid_time) tras += 1;
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valid_time = (boot_config.rcd * 1000000) / boot_config.mclk;
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new_time = (rcd * 1000000) / new_mclk;
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if (new_time < valid_time) rcd += 1;
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valid_time = (boot_config.tpc * 1000000) / boot_config.mclk;
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new_time = (tpc * 1000000) / new_mclk;
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if (new_time < valid_time) tpc += 1;
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valid_time = (boot_config.trwl * 1000000) / boot_config.mclk;
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new_time = (trwl * 1000000) / new_mclk;
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if (new_time < valid_time) trwl += 1;
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valid_time = (boot_config.trc * 1000000) / boot_config.mclk;
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new_time = (trc * 1000000) / new_mclk;
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if (new_time < valid_time) trc += 2;
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tras = (tras < 4) ? 4: tras;
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tras = (tras > 11) ? 11: tras;
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tras -= 4;
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rcd = (rcd < 1) ? 1: rcd;
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rcd = (rcd > 4) ? 4: rcd;
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rcd -= 1;
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tpc = (tpc < 1) ? 1: tpc;
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tpc = (tpc > 8) ? 8: tpc;
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tpc -= 1;
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trwl = (trwl < 1) ? 1: trwl;
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trwl = (trwl > 4) ? 4: trwl;
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trwl -= 1;
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trc = (trc < 1) ? 1: trc;
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trc = (trc > 15) ? 15: trc;
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trc /= 2;
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dmcr = REG_EMC_DMCR;
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dmcr &= ~(EMC_DMCR_TRAS_MASK | EMC_DMCR_RCD_MASK | EMC_DMCR_TPC_MASK | EMC_DMCR_TRWL_MASK | EMC_DMCR_TRC_MASK);
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dmcr |= ((tras << EMC_DMCR_TRAS_BIT) | (rcd << EMC_DMCR_RCD_BIT) | (tpc << EMC_DMCR_TPC_BIT) | (trwl << EMC_DMCR_TRWL_BIT) | (trc << EMC_DMCR_TRC_BIT));
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REG_EMC_DMCR = dmcr;
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}
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static void jz_update_dram_prev(unsigned int cur_mclk, unsigned int new_mclk)
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{
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/* No risk, no fun: run with interrupts on! */
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if (new_mclk > cur_mclk) {
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/* We're going FASTER, so first update TRAS, RCD, TPC, TRWL
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* and TRC of DMCR before changing the frequency.
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*/
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jz_update_dram_dmcr(new_mclk);
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} else {
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/* We're going SLOWER: first update RTCOR value
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* before changing the frequency.
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*/
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jz_update_dram_rtcor(new_mclk);
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}
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}
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static void jz_update_dram_post(unsigned int cur_mclk, unsigned int new_mclk)
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{
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/* No risk, no fun: run with interrupts on! */
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if (new_mclk > cur_mclk) {
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/* We're going FASTER, so update RTCOR
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* after changing the frequency
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*/
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jz_update_dram_rtcor(new_mclk);
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} else {
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/* We're going SLOWER: so update TRAS, RCD, TPC, TRWL
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* and TRC of DMCR after changing the frequency.
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*/
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jz_update_dram_dmcr(new_mclk);
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}
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}
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static void jz_scale_divisors(struct dpm_regs *regs)
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{
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unsigned int cpccr;
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unsigned int cur_mclk, new_mclk;
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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unsigned int tmp = 0, wait = PLL_WAIT_500NS;
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cpccr = REG_CPM_CPCCR;
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cpccr &= ~((unsigned long)regs->cpccr_mask);
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cpccr |= regs->cpccr;
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cpccr |= CPM_CPCCR_CE; /* update immediately */
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cur_mclk = __cpm_get_mclk();
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new_mclk = __cpm_get_pllout() / div[(cpccr & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT];
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/* Update some DRAM parameters before changing frequency */
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jz_update_dram_prev(cur_mclk, new_mclk);
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/* update register to change the clocks.
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* align this code to a cache line.
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*/
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__asm__ __volatile__(
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".set noreorder\n\t"
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".align 5\n"
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"sw %1,0(%0)\n\t"
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"li %3,0\n\t"
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"1:\n\t"
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"bne %3,%2,1b\n\t"
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"addi %3, 1\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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".set reorder\n\t"
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:
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: "r" (CPM_CPCCR), "r" (cpccr), "r" (wait), "r" (tmp));
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/* Update some other DRAM parameters after changing frequency */
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jz_update_dram_post(cur_mclk, new_mclk);
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}
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#ifdef CHANGE_PLL
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/* Maintain the LCD clock and pixel clock */
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static void jz_scale_lcd_divisors(struct dpm_regs *regs)
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{
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unsigned int new_pll, new_lcd_div, new_lcdpix_div;
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unsigned int cpccr;
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unsigned int tmp = 0, wait = PLL_WAIT_500NS;
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if (!boot_config.lcd_clks_initialized) return;
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new_pll = __cpm_get_pllout();
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new_lcd_div = new_pll / boot_config.lcd_clk;
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new_lcdpix_div = new_pll / boot_config.lcdpix_clk;
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if (new_lcd_div < 1)
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new_lcd_div = 1;
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if (new_lcd_div > 16)
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new_lcd_div = 16;
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if (new_lcdpix_div < 1)
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new_lcdpix_div = 1;
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if (new_lcdpix_div > 512)
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new_lcdpix_div = 512;
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// REG_CPM_CPCCR2 = new_lcdpix_div - 1;
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cpccr = REG_CPM_CPCCR;
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cpccr &= ~CPM_CPCCR_LDIV_MASK;
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cpccr |= ((new_lcd_div - 1) << CPM_CPCCR_LDIV_BIT);
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cpccr |= CPM_CPCCR_CE; /* update immediately */
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/* update register to change the clocks.
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* align this code to a cache line.
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*/
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__asm__ __volatile__(
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".set noreorder\n\t"
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".align 5\n"
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"sw %1,0(%0)\n\t"
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"li %3,0\n\t"
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"1:\n\t"
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"bne %3,%2,1b\n\t"
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"addi %3, 1\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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".set reorder\n\t"
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:
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: "r" (CPM_CPCCR), "r" (cpccr), "r" (wait), "r" (tmp));
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}
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static void jz_scale_pll(struct dpm_regs *regs)
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{
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unsigned int cppcr;
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unsigned int cur_mclk, new_mclk, new_pll;
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int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
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int od[] = {1, 2, 2, 4};
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cppcr = REG_CPM_CPPCR;
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cppcr &= ~(regs->cppcr_mask | CPM_CPPCR_PLLS | CPM_CPPCR_PLLEN | CPM_CPPCR_PLLST_MASK);
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regs->cppcr &= ~CPM_CPPCR_PLLEN;
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cppcr |= (regs->cppcr | 0xff);
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/* Update some DRAM parameters before changing frequency */
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new_pll = JZ_EXTAL * ((cppcr>>23)+2) / ((((cppcr>>18)&0x1f)+2) * od[(cppcr>>16)&0x03]);
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cur_mclk = __cpm_get_mclk();
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new_mclk = new_pll / div[(REG_CPM_CPCCR>>CPM_CPCCR_MDIV_BIT) & 0xf];
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/*
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* Update some SDRAM parameters
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*/
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jz_update_dram_prev(cur_mclk, new_mclk);
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/*
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* Update PLL, align code to cache line.
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*/
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cppcr |= CPM_CPPCR_PLLEN;
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__asm__ __volatile__(
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".set noreorder\n\t"
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".align 5\n"
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"sw %1,0(%0)\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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".set reorder\n\t"
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:
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: "r" (CPM_CPPCR), "r" (cppcr));
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/* Update some other DRAM parameters after changing frequency */
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jz_update_dram_post(cur_mclk, new_mclk);
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}
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#endif
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static void jz4740_transition(struct dpm_regs *regs)
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{
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/*
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* Get and save some boot-time conditions.
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*/
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jz_init_boot_config();
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#ifdef CHANGE_PLL
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/*
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* Disable LCD before scaling pll.
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* LCD and LCD pixel clocks should not be changed even if the PLL
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* output frequency has been changed.
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*/
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REG_LCD_CTRL &= ~LCD_CTRL_ENA;
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/*
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* Stop module clocks before scaling PLL
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*/
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__cpm_stop_eth();
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__cpm_stop_aic(1);
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__cpm_stop_aic(2);
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#endif
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/* ... add more as necessary */
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if (regs->pll_up_flag == PLL_GOES_UP) {
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/* the pll frequency is going up, so change dividors first */
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jz_scale_divisors(regs);
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#ifdef CHANGE_PLL
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jz_scale_pll(regs);
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#endif
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}
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else if (regs->pll_up_flag == PLL_GOES_DOWN) {
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/* the pll frequency is going down, so change pll first */
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#ifdef CHANGE_PLL
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jz_scale_pll(regs);
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#endif
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jz_scale_divisors(regs);
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}
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else {
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/* the pll frequency is unchanged, so change divisors only */
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jz_scale_divisors(regs);
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}
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#ifdef CHANGE_PLL
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/*
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* Restart module clocks before scaling PLL
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*/
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__cpm_start_eth();
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__cpm_start_aic(1);
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__cpm_start_aic(2);
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/* ... add more as necessary */
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/* Scale the LCD divisors after scaling pll */
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if (regs->pll_up_flag != PLL_UNCHANGED) {
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jz_scale_lcd_divisors(regs);
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}
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/* Enable LCD controller */
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REG_LCD_CTRL &= ~LCD_CTRL_DIS;
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REG_LCD_CTRL |= LCD_CTRL_ENA;
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#endif
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/* Update system clocks */
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jz_update_clocks();
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}
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extern unsigned int idle_times;
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static unsigned int jz4740_freq_get(unsigned int cpu)
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{
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return (__cpm_get_cclk() / 1000);
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}
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static unsigned int index_to_divisor(unsigned int index, struct dpm_regs *regs)
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{
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int n2FR[33] = {
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0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
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7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
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9
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};
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int div[4] = {1, 2, 2, 2}; /* divisors of I:S:P:M */
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unsigned int div_of_cclk, new_freq, i;
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regs->pll_up_flag = PLL_UNCHANGED;
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regs->cpccr_mask = CPM_CPCCR_CDIV_MASK | CPM_CPCCR_HDIV_MASK | CPM_CPCCR_PDIV_MASK | CPM_CPCCR_MDIV_MASK;
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new_freq = jz4740_freq_table.table[index].frequency;
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do {
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div_of_cclk = __cpm_get_pllout() / (1000 * new_freq);
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} while (div_of_cclk==0);
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if(div_of_cclk == 1 || div_of_cclk == 2 || div_of_cclk == 4) {
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for(i = 1; i<4; i++) {
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div[i] = 3;
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}
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} else {
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|
for(i = 1; i<4; i++) {
|
|
div[i] = 2;
|
|
}
|
|
}
|
|
|
|
for(i = 0; i<4; i++) {
|
|
div[i] *= div_of_cclk;
|
|
}
|
|
|
|
dprintk("divisors of I:S:P:M = %d:%d:%d:%d\n", div[0], div[1], div[2], div[3]);
|
|
|
|
regs->cpccr =
|
|
(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
|
|
(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
|
|
(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
|
|
(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT);
|
|
|
|
return div_of_cclk;
|
|
}
|
|
|
|
static void jz4740_set_cpu_divider_index(unsigned int cpu, unsigned int index)
|
|
{
|
|
unsigned long divisor, old_divisor;
|
|
struct cpufreq_freqs freqs;
|
|
struct dpm_regs regs;
|
|
|
|
old_divisor = __cpm_get_pllout() / __cpm_get_cclk();
|
|
divisor = index_to_divisor(index, ®s);
|
|
|
|
freqs.old = __cpm_get_cclk() / 1000;
|
|
freqs.new = __cpm_get_pllout() / (1000 * divisor);
|
|
freqs.cpu = cpu;
|
|
|
|
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
|
|
|
|
if (old_divisor != divisor)
|
|
jz4740_transition(®s);
|
|
|
|
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
|
|
}
|
|
|
|
static int jz4740_freq_target(struct cpufreq_policy *policy,
|
|
unsigned int target_freq,
|
|
unsigned int relation)
|
|
{
|
|
unsigned int new_index = 0;
|
|
|
|
if (cpufreq_frequency_table_target(policy,
|
|
&jz4740_freq_table.table[0],
|
|
target_freq, relation, &new_index))
|
|
return -EINVAL;
|
|
|
|
jz4740_set_cpu_divider_index(policy->cpu, new_index);
|
|
|
|
dprintk("new frequency is %d KHz (REG_CPM_CPCCR:0x%x)\n", __cpm_get_cclk() / 1000, REG_CPM_CPCCR);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int jz4740_freq_verify(struct cpufreq_policy *policy)
|
|
{
|
|
return cpufreq_frequency_table_verify(policy,
|
|
&jz4740_freq_table.table[0]);
|
|
}
|
|
|
|
static int __init jz4740_cpufreq_driver_init(struct cpufreq_policy *policy)
|
|
{
|
|
|
|
struct cpufreq_frequency_table *table = &jz4740_freq_table.table[0];
|
|
unsigned int MAX_FREQ;
|
|
|
|
dprintk(KERN_INFO "Jz4740 cpufreq driver\n");
|
|
|
|
if (policy->cpu != 0)
|
|
return -EINVAL;
|
|
|
|
policy->cur = MAX_FREQ = __cpm_get_cclk() / 1000; /* in kHz. Current and max frequency is determined by u-boot */
|
|
policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
|
|
|
|
policy->cpuinfo.min_freq = MAX_FREQ/8;
|
|
policy->cpuinfo.max_freq = MAX_FREQ;
|
|
policy->cpuinfo.transition_latency = 100000; /* in 10^(-9) s = nanoseconds */
|
|
|
|
table[0].index = 0;
|
|
table[0].frequency = MAX_FREQ/8;
|
|
table[1].index = 1;
|
|
table[1].frequency = MAX_FREQ/6;
|
|
table[2].index = 2;
|
|
table[2].frequency = MAX_FREQ/4;
|
|
table[3].index = 3;
|
|
table[3].frequency = MAX_FREQ/3;
|
|
table[4].index = 4;
|
|
table[4].frequency = MAX_FREQ/2;
|
|
table[5].index = 5;
|
|
table[5].frequency = MAX_FREQ;
|
|
table[6].index = 6;
|
|
table[6].frequency = CPUFREQ_TABLE_END;
|
|
|
|
#ifdef CONFIG_CPU_FREQ_STAT_DETAILS
|
|
cpufreq_frequency_table_get_attr(table, policy->cpu); /* for showing /sys/devices/system/cpu/cpuX/cpufreq/stats/ */
|
|
#endif
|
|
|
|
return cpufreq_frequency_table_cpuinfo(policy, table);
|
|
}
|
|
|
|
static struct cpufreq_driver cpufreq_jz4740_driver = {
|
|
// .flags = CPUFREQ_STICKY,
|
|
.init = jz4740_cpufreq_driver_init,
|
|
.verify = jz4740_freq_verify,
|
|
.target = jz4740_freq_target,
|
|
.get = jz4740_freq_get,
|
|
.name = "jz4740",
|
|
};
|
|
|
|
static int __init jz4740_cpufreq_init(void)
|
|
{
|
|
return cpufreq_register_driver(&cpufreq_jz4740_driver);
|
|
}
|
|
|
|
static void __exit jz4740_cpufreq_exit(void)
|
|
{
|
|
cpufreq_unregister_driver(&cpufreq_jz4740_driver);
|
|
}
|
|
|
|
module_init(jz4740_cpufreq_init);
|
|
module_exit(jz4740_cpufreq_exit);
|
|
|
|
MODULE_AUTHOR("Regen <lhhuang@ingenic.cn>");
|
|
MODULE_DESCRIPTION("cpufreq driver for Jz4740");
|
|
MODULE_LICENSE("GPL");
|
|
|