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8b22e86996
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@23939 3c298f89-4303-0410-b956-a3cf2f4a3e73
87 lines
2.6 KiB
Diff
87 lines
2.6 KiB
Diff
From 3924996bab2845bdf9a9d16ff7c20445de1ab55d Mon Sep 17 00:00:00 2001
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From: Nicolas Pitre <nico@fluxnic.net>
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Date: Thu, 21 Oct 2010 15:48:33 -0400
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Subject: [PATCH] [ARM] Kirkwood: restrict the scope of the PCIe reset workaround
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Commit 21f0ba90a447 "orion/kirkwood: reset PCIe unit on boot" made the
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reset of the PCIe unit unconditional. While this may fix problems on some
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targets, this also causes problems on other targets.
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Saeed Bishara <saeed@marvell.com> said about the original problem: "We
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couln't pinpoint the root cause of this issue, actually we failed to
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reproduce that issue."
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So let's restrict the reset of the PCIe unit only to the target where
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the original problem was observed.
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Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
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---
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arch/arm/mach-kirkwood/ts41x-setup.c | 14 +++++++++++++-
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arch/arm/plat-orion/include/plat/pcie.h | 3 +++
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arch/arm/plat-orion/pcie.c | 5 -----
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3 files changed, 16 insertions(+), 6 deletions(-)
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--- a/arch/arm/mach-kirkwood/ts41x-setup.c
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+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
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@@ -27,6 +27,10 @@
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#include "mpp.h"
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#include "tsx1x-common.h"
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+/* for the PCIe reset workaround */
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+#include <plat/pcie.h>
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+
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+
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#define QNAP_TS41X_JUMPER_JP1 45
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static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = {
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@@ -140,8 +144,16 @@ static void __init qnap_ts41x_init(void)
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static int __init ts41x_pci_init(void)
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{
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- if (machine_is_ts41x())
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+ if (machine_is_ts41x()) {
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+ /*
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+ * Without this explicit reset, the PCIe SATA controller
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+ * (Marvell 88sx7042/sata_mv) is known to stop working
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+ * after a few minutes.
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+ */
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+ orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
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+
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kirkwood_pcie_init(KW_PCIE0);
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+ }
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return 0;
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}
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--- a/arch/arm/plat-orion/include/plat/pcie.h
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+++ b/arch/arm/plat-orion/include/plat/pcie.h
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@@ -11,12 +11,15 @@
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#ifndef __PLAT_PCIE_H
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#define __PLAT_PCIE_H
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+struct pci_bus;
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+
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u32 orion_pcie_dev_id(void __iomem *base);
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u32 orion_pcie_rev(void __iomem *base);
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int orion_pcie_link_up(void __iomem *base);
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int orion_pcie_x4_mode(void __iomem *base);
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int orion_pcie_get_local_bus_nr(void __iomem *base);
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void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
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+void orion_pcie_reset(void __iomem *base);
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void orion_pcie_setup(void __iomem *base,
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struct mbus_dram_target_info *dram);
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int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
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--- a/arch/arm/plat-orion/pcie.c
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+++ b/arch/arm/plat-orion/pcie.c
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@@ -182,11 +182,6 @@ void __init orion_pcie_setup(void __iome
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u32 mask;
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/*
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- * soft reset PCIe unit
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- */
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- orion_pcie_reset(base);
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-
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- /*
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* Point PCIe unit MBUS decode windows to DRAM space.
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*/
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orion_pcie_setup_wins(base, dram);
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