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df88996997
The nand subtarget is not working yet. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33983 3c298f89-4303-0410-b956-a3cf2f4a3e73
104 lines
3.1 KiB
Diff
104 lines
3.1 KiB
Diff
From 8bb54348722216a1dd6905d9d031ebdaa3a544a4 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Sun, 24 Jun 2012 23:05:20 +0200
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Subject: [PATCH 26/34] MIPS: ath79: add PCI controller registration code for the QCA9558 SoC
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---
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arch/mips/ath79/Kconfig | 2 +
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arch/mips/ath79/pci.c | 36 ++++++++++++++++++++++++
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 13 ++++++++
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3 files changed, 51 insertions(+), 0 deletions(-)
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--- a/arch/mips/ath79/Kconfig
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+++ b/arch/mips/ath79/Kconfig
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@@ -90,6 +90,8 @@ config SOC_AR934X
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config SOC_QCA955X
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select USB_ARCH_HAS_EHCI
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+ select HW_HAS_PCI
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+ select PCI_AR724X if PCI
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def_bool n
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config PCI_AR724X
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--- a/arch/mips/ath79/pci.c
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+++ b/arch/mips/ath79/pci.c
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@@ -49,6 +49,21 @@ static const struct ath79_pci_irq ar724x
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}
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};
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+static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {
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+ {
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+ .bus = 0,
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+ .slot = 0,
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+ .pin = 1,
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+ .irq = ATH79_PCI_IRQ(0),
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+ },
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+ {
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+ .bus = 1,
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+ .slot = 0,
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+ .pin = 1,
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+ .irq = ATH79_PCI_IRQ(1),
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+ },
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+};
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+
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int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
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{
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int irq = -1;
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@@ -64,6 +79,9 @@ int __init pcibios_map_irq(const struct
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soc_is_ar9344()) {
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ath79_pci_irq_map = ar724x_pci_irq_map;
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ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
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+ } else if (soc_is_qca955x()) {
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+ ath79_pci_irq_map = qca955x_pci_irq_map;
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+ ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
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} else {
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pr_crit("pci %s: invalid irq map\n",
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pci_name((struct pci_dev *) dev));
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@@ -215,6 +233,24 @@ int __init ath79_register_pci(void)
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AR724X_PCI_MEM_SIZE,
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0,
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ATH79_IP2_IRQ(0));
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+ } else if (soc_is_qca9558()) {
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+ pdev = ath79_register_pci_ar724x(0,
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+ QCA955X_PCI_CFG_BASE0,
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+ QCA955X_PCI_CTRL_BASE0,
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+ QCA955X_PCI_CRP_BASE0,
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+ QCA955X_PCI_MEM_BASE0,
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+ QCA955X_PCI_MEM_SIZE,
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+ 0,
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+ ATH79_IP2_IRQ(0));
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+
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+ pdev = ath79_register_pci_ar724x(1,
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+ QCA955X_PCI_CFG_BASE1,
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+ QCA955X_PCI_CTRL_BASE1,
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+ QCA955X_PCI_CRP_BASE1,
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+ QCA955X_PCI_MEM_BASE1,
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+ QCA955X_PCI_MEM_SIZE,
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+ 1,
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+ ATH79_IP3_IRQ(2));
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} else {
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/* No PCI support */
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return -ENODEV;
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -94,6 +94,19 @@
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#define AR934X_EHCI_BASE 0x1b000000
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#define AR934X_EHCI_SIZE 0x200
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+#define QCA955X_PCI_MEM_BASE0 0x10000000
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+#define QCA955X_PCI_MEM_BASE1 0x12000000
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+#define QCA955X_PCI_MEM_SIZE 0x02000000
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+#define QCA955X_PCI_CFG_BASE0 0x14000000
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+#define QCA955X_PCI_CFG_BASE1 0x16000000
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+#define QCA955X_PCI_CFG_SIZE 0x1000
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+#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
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+#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
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+#define QCA955X_PCI_CRP_SIZE 0x1000
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+#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
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+#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
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+#define QCA955X_PCI_CTRL_SIZE 0x100
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+
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#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define QCA955X_WMAC_SIZE 0x20000
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#define QCA955X_EHCI0_BASE 0x1b000000
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