mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-05 11:40:37 +02:00
e0b80e41eb
Tested on the following boards: ALFA AP96 TL-MR3220 v1 TL-WR1043ND v1 TL-WR2543ND v1 TL-WR703N v1 TL-WR741ND v1 TL-WR741ND v4 WNDR3700 v1 WZR-HP-G300NH git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29868 3c298f89-4303-0410-b956-a3cf2f4a3e73
232 lines
7.8 KiB
Diff
232 lines
7.8 KiB
Diff
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -20,7 +20,13 @@
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#include <linux/io.h>
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#include <linux/bitops.h>
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+#define AR71XX_PCI_MEM_BASE 0x10000000
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+#define AR71XX_PCI_MEM_SIZE 0x08000000
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#define AR71XX_APB_BASE 0x18000000
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+#define AR71XX_GE0_BASE 0x19000000
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+#define AR71XX_GE0_SIZE 0x10000
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+#define AR71XX_GE1_BASE 0x1a000000
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+#define AR71XX_GE1_SIZE 0x10000
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#define AR71XX_EHCI_BASE 0x1b000000
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#define AR71XX_EHCI_SIZE 0x1000
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#define AR71XX_OHCI_BASE 0x1c000000
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@@ -40,6 +46,8 @@
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#define AR71XX_PLL_SIZE 0x100
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#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
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#define AR71XX_RESET_SIZE 0x100
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+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
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+#define AR71XX_MII_SIZE 0x100
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#define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
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#define AR7240_USB_CTRL_SIZE 0x100
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@@ -56,11 +64,15 @@
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#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
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#define AR933X_UART_SIZE 0x14
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+#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
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+#define AR933X_GMAC_SIZE 0x04
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#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define AR933X_WMAC_SIZE 0x20000
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#define AR933X_EHCI_BASE 0x1b000000
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#define AR933X_EHCI_SIZE 0x1000
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+#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
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+#define AR934X_GMAC_SIZE 0x14
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#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
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#define AR934X_WMAC_SIZE 0x20000
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#define AR934X_EHCI_BASE 0x1b000000
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@@ -120,6 +132,9 @@
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#define AR71XX_AHB_DIV_SHIFT 20
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#define AR71XX_AHB_DIV_MASK 0x7
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+#define AR71XX_ETH0_PLL_SHIFT 17
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+#define AR71XX_ETH1_PLL_SHIFT 19
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+
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#define AR724X_PLL_REG_CPU_CONFIG 0x00
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#define AR724X_PLL_REG_PCIE_CONFIG 0x18
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@@ -132,6 +147,8 @@
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#define AR724X_DDR_DIV_SHIFT 22
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#define AR724X_DDR_DIV_MASK 0x3
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+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
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+
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#define AR913X_PLL_REG_CPU_CONFIG 0x00
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#define AR913X_PLL_REG_ETH_CONFIG 0x04
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#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
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@@ -144,6 +161,9 @@
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#define AR913X_AHB_DIV_SHIFT 19
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#define AR913X_AHB_DIV_MASK 0x1
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+#define AR913X_ETH0_PLL_SHIFT 20
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+#define AR913X_ETH1_PLL_SHIFT 22
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+
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#define AR933X_PLL_CPU_CONFIG_REG 0x00
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#define AR933X_PLL_CLOCK_CTRL_REG 0x08
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@@ -285,7 +305,11 @@
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#define AR913X_RESET_USB_HOST BIT(5)
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#define AR913X_RESET_USB_PHY BIT(4)
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+#define AR933X_RESET_GE1_MDIO BIT(23)
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+#define AR933X_RESET_GE0_MDIO BIT(22)
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+#define AR933X_RESET_GE1_MAC BIT(13)
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#define AR933X_RESET_WMAC BIT(11)
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+#define AR933X_RESET_GE0_MAC BIT(9)
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#define AR933X_RESET_USB_HOST BIT(5)
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#define AR933X_RESET_USB_PHY BIT(4)
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#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
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@@ -323,6 +347,8 @@
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#define AR934X_RESET_MBOX BIT(1)
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#define AR934X_RESET_I2S BIT(0)
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+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
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+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
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#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
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#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
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@@ -427,6 +453,14 @@
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#define AR71XX_GPIO_REG_INT_ENABLE 0x24
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#define AR71XX_GPIO_REG_FUNC 0x28
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+#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
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+#define AR934X_GPIO_REG_OUT_FUNC1 0x30
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+#define AR934X_GPIO_REG_OUT_FUNC2 0x34
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+#define AR934X_GPIO_REG_OUT_FUNC3 0x38
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+#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
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+#define AR934X_GPIO_REG_OUT_FUNC5 0x40
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+#define AR934X_GPIO_REG_FUNC 0x6c
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+
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#define AR71XX_GPIO_COUNT 16
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#define AR7240_GPIO_COUNT 18
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#define AR7241_GPIO_COUNT 20
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@@ -434,4 +468,124 @@
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#define AR933X_GPIO_COUNT 30
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#define AR934X_GPIO_COUNT 23
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+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
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+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
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+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
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+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
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+#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
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+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
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+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
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+
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+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
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+#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
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+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
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+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
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+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
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+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
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+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
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+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
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+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
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+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
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+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
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+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
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+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
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+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
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+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
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+#define AR724X_GPIO_FUNC_UART_EN BIT(1)
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+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
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+
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+#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
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+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
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+#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
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+#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
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+#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
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+#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
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+#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
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+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
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+#define AR913X_GPIO_FUNC_UART_EN BIT(8)
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+#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
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+
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+#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
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+#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
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+#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
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+#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
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+#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
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+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
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+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
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+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
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+#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
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+#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
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+#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
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+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
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+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
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+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
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+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
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+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
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+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
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+#define AR933X_GPIO_FUNC_UART_EN BIT(1)
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+#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
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+
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+#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17)
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+#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14)
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+#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13)
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+
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+#define AR934X_GPIO_OUT_GPIO 0x00
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+
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+/*
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+ * MII_CTRL block
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+ */
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+#define AR71XX_MII_REG_MII0_CTRL 0x00
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+#define AR71XX_MII_REG_MII1_CTRL 0x04
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+
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+#define AR71XX_MII_CTRL_IF_MASK 3
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+#define AR71XX_MII_CTRL_SPEED_SHIFT 4
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+#define AR71XX_MII_CTRL_SPEED_MASK 3
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+#define AR71XX_MII_CTRL_SPEED_10 0
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+#define AR71XX_MII_CTRL_SPEED_100 1
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+#define AR71XX_MII_CTRL_SPEED_1000 2
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+
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+#define AR71XX_MII0_CTRL_IF_GMII 0
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+#define AR71XX_MII0_CTRL_IF_MII 1
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+#define AR71XX_MII0_CTRL_IF_RGMII 2
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+#define AR71XX_MII0_CTRL_IF_RMII 3
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+
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+#define AR71XX_MII1_CTRL_IF_RGMII 0
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+#define AR71XX_MII1_CTRL_IF_RMII 1
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+
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+/*
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+ * AR933X GMAC interface
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+ */
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+#define AR933X_GMAC_REG_ETH_CFG 0x00
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+
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+#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
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+#define AR933X_ETH_CFG_MII_GE0 BIT(1)
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+#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
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+#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
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+#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
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+#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
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+#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
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+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
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+#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
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+#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
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+#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
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+
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+/*
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+ * AR934X GMAC Interface
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+ */
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+#define AR934X_GMAC_REG_ETH_CFG 0x00
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+
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+#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
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+#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
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+#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
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+#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
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+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
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+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
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+#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
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+#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
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+#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
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+#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
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+#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
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+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
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+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
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+
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#endif /* __ASM_MACH_AR71XX_REGS_H */
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