mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34061 3c298f89-4303-0410-b956-a3cf2f4a3e73
196 lines
6.4 KiB
Diff
196 lines
6.4 KiB
Diff
From 61fa969f27ec58296544bf94d058f3aa704cb8d9 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 16 Aug 2012 11:39:57 +0000
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Subject: [PATCH 2/9] MIPS: lantiq: split up IRQ IM ranges
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Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate
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the SVIP we need to support IM ranges that are scattered inside the register range.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/4237/
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---
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.../include/asm/mach-lantiq/falcon/falcon_irq.h | 2 +
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.../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 2 +
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arch/mips/lantiq/irq.c | 60 +++++++++++---------
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3 files changed, 36 insertions(+), 28 deletions(-)
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diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
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index 318f982..c6b63a4 100644
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--- a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
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+++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
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@@ -20,4 +20,6 @@
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#define MIPS_CPU_TIMER_IRQ 7
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+#define MAX_IM 5
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+
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#endif /* _FALCON_IRQ__ */
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diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
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index aa0b3b8..5eadfe5 100644
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--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
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@@ -21,4 +21,6 @@
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#define MIPS_CPU_TIMER_IRQ 7
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+#define MAX_IM 5
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+
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#endif
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diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
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index 57c1a4e..a2699a70 100644
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--- a/arch/mips/lantiq/irq.c
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+++ b/arch/mips/lantiq/irq.c
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@@ -55,8 +55,8 @@
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*/
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#define LTQ_ICU_EBU_IRQ 22
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-#define ltq_icu_w32(x, y) ltq_w32((x), ltq_icu_membase + (y))
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-#define ltq_icu_r32(x) ltq_r32(ltq_icu_membase + (x))
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+#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
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+#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
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#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
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#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
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@@ -82,17 +82,17 @@ static unsigned short ltq_eiu_irq[MAX_EIU] = {
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};
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static int exin_avail;
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-static void __iomem *ltq_icu_membase;
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+static void __iomem *ltq_icu_membase[MAX_IM];
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static void __iomem *ltq_eiu_membase;
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void ltq_disable_irq(struct irq_data *d)
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{
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u32 ier = LTQ_ICU_IM0_IER;
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int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
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+ int im = offset / INT_NUM_IM_OFFSET;
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- ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
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offset %= INT_NUM_IM_OFFSET;
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- ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier);
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+ ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
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}
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void ltq_mask_and_ack_irq(struct irq_data *d)
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@@ -100,32 +100,31 @@ void ltq_mask_and_ack_irq(struct irq_data *d)
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u32 ier = LTQ_ICU_IM0_IER;
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u32 isr = LTQ_ICU_IM0_ISR;
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int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
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+ int im = offset / INT_NUM_IM_OFFSET;
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- ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
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- isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
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offset %= INT_NUM_IM_OFFSET;
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- ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier);
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- ltq_icu_w32(BIT(offset), isr);
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+ ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
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+ ltq_icu_w32(im, BIT(offset), isr);
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}
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static void ltq_ack_irq(struct irq_data *d)
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{
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u32 isr = LTQ_ICU_IM0_ISR;
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int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
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+ int im = offset / INT_NUM_IM_OFFSET;
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- isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
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offset %= INT_NUM_IM_OFFSET;
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- ltq_icu_w32(BIT(offset), isr);
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+ ltq_icu_w32(im, BIT(offset), isr);
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}
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void ltq_enable_irq(struct irq_data *d)
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{
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u32 ier = LTQ_ICU_IM0_IER;
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int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
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+ int im = offset / INT_NUM_IM_OFFSET;
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- ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
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offset %= INT_NUM_IM_OFFSET;
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- ltq_icu_w32(ltq_icu_r32(ier) | BIT(offset), ier);
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+ ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
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}
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static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
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@@ -192,7 +191,7 @@ static void ltq_hw_irqdispatch(int module)
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{
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u32 irq;
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- irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET));
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+ irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
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if (irq == 0)
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return;
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@@ -275,7 +274,7 @@ asmlinkage void plat_irq_dispatch(void)
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do_IRQ(MIPS_CPU_TIMER_IRQ);
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goto out;
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} else {
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- for (i = 0; i < 5; i++) {
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+ for (i = 0; i < MAX_IM; i++) {
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if (pending & (CAUSEF_IP2 << i)) {
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ltq_hw_irqdispatch(i);
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goto out;
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@@ -318,15 +317,19 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
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struct resource res;
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int i;
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- if (of_address_to_resource(node, 0, &res))
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- panic("Failed to get icu memory range");
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+ for (i = 0; i < MAX_IM; i++) {
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+ if (of_address_to_resource(node, i, &res))
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+ panic("Failed to get icu memory range");
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- if (request_mem_region(res.start, resource_size(&res), res.name) < 0)
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- pr_err("Failed to request icu memory");
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+ if (request_mem_region(res.start, resource_size(&res),
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+ res.name) < 0)
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+ pr_err("Failed to request icu memory");
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- ltq_icu_membase = ioremap_nocache(res.start, resource_size(&res));
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- if (!ltq_icu_membase)
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- panic("Failed to remap icu memory");
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+ ltq_icu_membase[i] = ioremap_nocache(res.start,
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+ resource_size(&res));
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+ if (!ltq_icu_membase[i])
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+ panic("Failed to remap icu memory");
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+ }
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/* the external interrupts are optional and xway only */
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eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
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@@ -351,17 +354,17 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
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}
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/* turn off all irqs by default */
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- for (i = 0; i < 5; i++) {
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+ for (i = 0; i < MAX_IM; i++) {
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/* make sure all irqs are turned off by default */
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- ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));
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+ ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
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/* clear all possibly pending interrupts */
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- ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
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+ ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
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}
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mips_cpu_irq_init();
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- for (i = 2; i <= 6; i++)
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- setup_irq(i, &cascade);
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+ for (i = 0; i < MAX_IM; i++)
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+ setup_irq(i + 2, &cascade);
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if (cpu_has_vint) {
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pr_info("Setting up vectored interrupts\n");
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@@ -373,7 +376,8 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
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set_vi_handler(7, ltq_hw5_irqdispatch);
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}
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- irq_domain_add_linear(node, 6 * INT_NUM_IM_OFFSET,
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+ irq_domain_add_linear(node,
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+ (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
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&irq_domain_ops, 0);
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#if defined(CONFIG_MIPS_MT_SMP)
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--
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1.7.10.4
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