mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-20 11:30:15 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34061 3c298f89-4303-0410-b956-a3cf2f4a3e73
555 lines
17 KiB
Diff
555 lines
17 KiB
Diff
From e316cb2b16bbfbe48387b56e7e6b5d32ec686f82 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 20 May 2012 00:33:56 +0200
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Subject: [PATCH 11/15] OF: pinctrl: MIPS: lantiq: adds support for FALCON SoC
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Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks
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of up to 32 pins.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
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Acked-by: Linus Walleij <linus.walleij@linaro.org>
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Cc: devicetree-discuss@lists.ozlabs.org
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Cc: linux-kernel@vger.kernel.org
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---
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.../include/asm/mach-lantiq/falcon/lantiq_soc.h | 4 +
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arch/mips/lantiq/Kconfig | 1 +
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drivers/pinctrl/Kconfig | 5 +
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drivers/pinctrl/Makefile | 1 +
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drivers/pinctrl/pinctrl-falcon.c | 468 ++++++++++++++++++++
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5 files changed, 479 insertions(+)
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create mode 100644 drivers/pinctrl/pinctrl-falcon.c
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diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
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index b385252..fccac35 100644
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--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
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+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
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@@ -57,6 +57,10 @@ extern __iomem void *ltq_sys1_membase;
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#define ltq_sys1_w32_mask(clear, set, reg) \
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ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
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+/* allow the gpio and pinctrl drivers to talk to eachother */
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+extern int pinctrl_falcon_get_range_size(int id);
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+extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range);
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+
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/*
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* to keep the irq code generic we need to define this to 0 as falcon
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* has no EIU/EBU
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diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
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index 080c013..d84f361 100644
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--- a/arch/mips/lantiq/Kconfig
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+++ b/arch/mips/lantiq/Kconfig
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@@ -20,6 +20,7 @@ config SOC_XWAY
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config SOC_FALCON
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bool "FALCON"
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+ select PINCTRL_FALCON
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endchoice
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diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
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index f77dce0..45d2158 100644
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--- a/drivers/pinctrl/Kconfig
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+++ b/drivers/pinctrl/Kconfig
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@@ -65,6 +65,11 @@ config PINCTRL_PXA3xx
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bool
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select PINMUX
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+config PINCTRL_FALCON
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+ bool
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+ depends on SOC_FALCON
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+ depends on PINCTRL_LANTIQ
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+
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config PINCTRL_MMP2
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bool "MMP2 pin controller driver"
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depends on ARCH_MMP
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diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
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index e19e207..c0566c8 100644
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--- a/drivers/pinctrl/Makefile
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+++ b/drivers/pinctrl/Makefile
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@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
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obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
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obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
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obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o
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+obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
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obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
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obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
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obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
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diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
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new file mode 100644
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index 0000000..ee73059
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--- /dev/null
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+++ b/drivers/pinctrl/pinctrl-falcon.c
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@@ -0,0 +1,468 @@
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+/*
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+ * linux/drivers/pinctrl/pinmux-falcon.c
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+ * based on linux/drivers/pinctrl/pinmux-pxa910.c
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
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+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/gpio.h>
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+#include <linux/interrupt.h>
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+#include <linux/slab.h>
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+#include <linux/export.h>
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+#include <linux/err.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/of_platform.h>
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+#include <linux/of_address.h>
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+#include <linux/of_gpio.h>
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+#include <linux/platform_device.h>
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+
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+#include "pinctrl-lantiq.h"
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+
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+#include <lantiq_soc.h>
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+
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+/* Multiplexer Control Register */
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+#define LTQ_PADC_MUX(x) (x * 0x4)
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+/* Pull Up Enable Register */
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+#define LTQ_PADC_PUEN 0x80
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+/* Pull Down Enable Register */
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+#define LTQ_PADC_PDEN 0x84
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+/* Slew Rate Control Register */
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+#define LTQ_PADC_SRC 0x88
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+/* Drive Current Control Register */
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+#define LTQ_PADC_DCC 0x8C
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+/* Pad Control Availability Register */
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+#define LTQ_PADC_AVAIL 0xF0
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+
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+#define pad_r32(p, reg) ltq_r32(p + reg)
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+#define pad_w32(p, val, reg) ltq_w32(val, p + reg)
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+#define pad_w32_mask(c, clear, set, reg) \
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+ pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg)
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+
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+#define pad_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
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+
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+#define PORTS 5
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+#define PINS 32
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+#define PORT(x) (x / PINS)
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+#define PORT_PIN(x) (x % PINS)
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+
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+#define MFP_FALCON(a, f0, f1, f2, f3) \
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+{ \
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+ .name = #a, \
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+ .pin = a, \
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+ .func = { \
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+ FALCON_MUX_##f0, \
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+ FALCON_MUX_##f1, \
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+ FALCON_MUX_##f2, \
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+ FALCON_MUX_##f3, \
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+ }, \
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+}
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+
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+#define GRP_MUX(a, m, p) \
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+{ \
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+ .name = a, \
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+ .mux = FALCON_MUX_##m, \
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+ .pins = p, \
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+ .npins = ARRAY_SIZE(p), \
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+}
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+
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+enum falcon_mux {
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+ FALCON_MUX_GPIO = 0,
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+ FALCON_MUX_RST,
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+ FALCON_MUX_NTR,
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+ FALCON_MUX_MDIO,
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+ FALCON_MUX_LED,
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+ FALCON_MUX_SPI,
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+ FALCON_MUX_ASC,
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+ FALCON_MUX_I2C,
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+ FALCON_MUX_HOSTIF,
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+ FALCON_MUX_SLIC,
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+ FALCON_MUX_JTAG,
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+ FALCON_MUX_PCM,
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+ FALCON_MUX_MII,
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+ FALCON_MUX_PHY,
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+ FALCON_MUX_NONE = 0xffff,
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+};
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+
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+static struct pinctrl_pin_desc falcon_pads[PORTS * PINS];
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+static int pad_count[PORTS];
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+
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+static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len)
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+{
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+ int base = bank * PINS;
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+ int i;
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+
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+ for (i = 0; i < len; i++) {
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+ /* strlen("ioXYZ") + 1 = 6 */
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+ char *name = kzalloc(6, GFP_KERNEL);
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+ snprintf(name, 6, "io%d", base + i);
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+ d[i].number = base + i;
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+ d[i].name = name;
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+ }
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+ pad_count[bank] = len;
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+}
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+
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+static struct ltq_mfp_pin falcon_mfp[] = {
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+ /* pin f0 f1 f2 f3 */
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+ MFP_FALCON(GPIO0, RST, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO1, GPIO, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO2, GPIO, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO3, GPIO, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO4, NTR, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO5, NTR, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO6, RST, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO7, MDIO, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO8, MDIO, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO9, LED, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO10, LED, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO11, LED, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO12, LED, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO13, LED, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO14, LED, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO32, ASC, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO33, ASC, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO34, SPI, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO35, SPI, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO36, SPI, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO37, SPI, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO38, SPI, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO39, I2C, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO40, I2C, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO41, HOSTIF, GPIO, HOSTIF, JTAG),
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+ MFP_FALCON(GPIO42, HOSTIF, GPIO, HOSTIF, NONE),
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+ MFP_FALCON(GPIO43, SLIC, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO44, SLIC, GPIO, PCM, ASC),
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+ MFP_FALCON(GPIO45, SLIC, GPIO, PCM, ASC),
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+ MFP_FALCON(GPIO64, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO65, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO66, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO67, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO68, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO69, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO70, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO71, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO72, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO73, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO74, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO75, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO76, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO77, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO78, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO79, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO80, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO81, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO82, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO83, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO84, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO85, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO86, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO87, MII, GPIO, NONE, NONE),
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+ MFP_FALCON(GPIO88, PHY, GPIO, NONE, NONE),
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+};
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+
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+static const unsigned pins_por[] = {GPIO0};
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+static const unsigned pins_ntr[] = {GPIO4};
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+static const unsigned pins_ntr8k[] = {GPIO5};
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+static const unsigned pins_hrst[] = {GPIO6};
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+static const unsigned pins_mdio[] = {GPIO7, GPIO8};
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+static const unsigned pins_bled[] = {GPIO7, GPIO10, GPIO11,
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+ GPIO12, GPIO13, GPIO14};
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+static const unsigned pins_asc0[] = {GPIO32, GPIO33};
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+static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36};
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+static const unsigned pins_spi_cs0[] = {GPIO37};
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+static const unsigned pins_spi_cs1[] = {GPIO38};
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+static const unsigned pins_i2c[] = {GPIO39, GPIO40};
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+static const unsigned pins_jtag[] = {GPIO41};
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+static const unsigned pins_slic[] = {GPIO43, GPIO44, GPIO45};
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+static const unsigned pins_pcm[] = {GPIO44, GPIO45};
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+static const unsigned pins_asc1[] = {GPIO44, GPIO45};
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+
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+static struct ltq_pin_group falcon_grps[] = {
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+ GRP_MUX("por", RST, pins_por),
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+ GRP_MUX("ntr", NTR, pins_ntr),
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+ GRP_MUX("ntr8k", NTR, pins_ntr8k),
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+ GRP_MUX("hrst", RST, pins_hrst),
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+ GRP_MUX("mdio", MDIO, pins_mdio),
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+ GRP_MUX("bootled", LED, pins_bled),
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+ GRP_MUX("asc0", ASC, pins_asc0),
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+ GRP_MUX("spi", SPI, pins_spi),
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+ GRP_MUX("spi cs0", SPI, pins_spi_cs0),
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+ GRP_MUX("spi cs1", SPI, pins_spi_cs1),
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+ GRP_MUX("i2c", I2C, pins_i2c),
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+ GRP_MUX("jtag", JTAG, pins_jtag),
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+ GRP_MUX("slic", SLIC, pins_slic),
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+ GRP_MUX("pcm", PCM, pins_pcm),
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+ GRP_MUX("asc1", ASC, pins_asc1),
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+};
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+
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+static const char * const ltq_rst_grps[] = {"por", "hrst"};
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+static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k"};
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+static const char * const ltq_mdio_grps[] = {"mdio"};
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+static const char * const ltq_bled_grps[] = {"bootled"};
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+static const char * const ltq_asc_grps[] = {"asc0", "asc1"};
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+static const char * const ltq_spi_grps[] = {"spi", "spi cs0", "spi cs1"};
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+static const char * const ltq_i2c_grps[] = {"i2c"};
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+static const char * const ltq_jtag_grps[] = {"jtag"};
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+static const char * const ltq_slic_grps[] = {"slic"};
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+static const char * const ltq_pcm_grps[] = {"pcm"};
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+
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+static struct ltq_pmx_func falcon_funcs[] = {
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+ {"rst", ARRAY_AND_SIZE(ltq_rst_grps)},
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+ {"ntr", ARRAY_AND_SIZE(ltq_ntr_grps)},
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+ {"mdio", ARRAY_AND_SIZE(ltq_mdio_grps)},
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+ {"led", ARRAY_AND_SIZE(ltq_bled_grps)},
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+ {"asc", ARRAY_AND_SIZE(ltq_asc_grps)},
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+ {"spi", ARRAY_AND_SIZE(ltq_spi_grps)},
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+ {"i2c", ARRAY_AND_SIZE(ltq_i2c_grps)},
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+ {"jtag", ARRAY_AND_SIZE(ltq_jtag_grps)},
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+ {"slic", ARRAY_AND_SIZE(ltq_slic_grps)},
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+ {"pcm", ARRAY_AND_SIZE(ltq_pcm_grps)},
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+};
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+
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+
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+
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+
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+/* --------- pinconf related code --------- */
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+static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev,
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+ unsigned group, unsigned long *config)
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+{
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+ return -ENOTSUPP;
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+}
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+
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+static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev,
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+ unsigned group, unsigned long config)
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+{
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+ return -ENOTSUPP;
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+}
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+
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+static int falcon_pinconf_get(struct pinctrl_dev *pctrldev,
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+ unsigned pin, unsigned long *config)
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+{
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+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
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+ enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
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+ void __iomem *mem = info->membase[PORT(pin)];
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+
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+ switch (param) {
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+ case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
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+ *config = LTQ_PINCONF_PACK(param,
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+ !!pad_getbit(mem, LTQ_PADC_DCC, PORT_PIN(pin)));
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+ break;
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+
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+ case LTQ_PINCONF_PARAM_SLEW_RATE:
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+ *config = LTQ_PINCONF_PACK(param,
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+ !!pad_getbit(mem, LTQ_PADC_SRC, PORT_PIN(pin)));
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+ break;
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+
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+ case LTQ_PINCONF_PARAM_PULL:
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+ if (pad_getbit(mem, LTQ_PADC_PDEN, PORT_PIN(pin)))
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+ *config = LTQ_PINCONF_PACK(param, 1);
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+ else if (pad_getbit(mem, LTQ_PADC_PUEN, PORT_PIN(pin)))
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+ *config = LTQ_PINCONF_PACK(param, 2);
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+ else
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+ *config = LTQ_PINCONF_PACK(param, 0);
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+
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+ break;
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+
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+ default:
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+ return -ENOTSUPP;
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+ }
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+
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+ return 0;
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+}
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+
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+static int falcon_pinconf_set(struct pinctrl_dev *pctrldev,
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+ unsigned pin, unsigned long config)
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+{
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+ enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config);
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+ int arg = LTQ_PINCONF_UNPACK_ARG(config);
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+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
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+ void __iomem *mem = info->membase[PORT(pin)];
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+ u32 reg;
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+
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+ switch (param) {
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+ case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
|
|
+ reg = LTQ_PADC_DCC;
|
|
+ break;
|
|
+
|
|
+ case LTQ_PINCONF_PARAM_SLEW_RATE:
|
|
+ reg = LTQ_PADC_SRC;
|
|
+ break;
|
|
+
|
|
+ case LTQ_PINCONF_PARAM_PULL:
|
|
+ if (arg == 1)
|
|
+ reg = LTQ_PADC_PDEN;
|
|
+ else
|
|
+ reg = LTQ_PADC_PUEN;
|
|
+ break;
|
|
+
|
|
+ default:
|
|
+ pr_err("%s: Invalid config param %04x\n",
|
|
+ pinctrl_dev_get_name(pctrldev), param);
|
|
+ return -ENOTSUPP;
|
|
+ }
|
|
+
|
|
+ pad_w32(mem, BIT(PORT_PIN(pin)), reg);
|
|
+ if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin))))
|
|
+ return -ENOTSUPP;
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev,
|
|
+ struct seq_file *s, unsigned offset)
|
|
+{
|
|
+}
|
|
+
|
|
+static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
|
|
+ struct seq_file *s, unsigned selector)
|
|
+{
|
|
+}
|
|
+
|
|
+struct pinconf_ops falcon_pinconf_ops = {
|
|
+ .pin_config_get = falcon_pinconf_get,
|
|
+ .pin_config_set = falcon_pinconf_set,
|
|
+ .pin_config_group_get = falcon_pinconf_group_get,
|
|
+ .pin_config_group_set = falcon_pinconf_group_set,
|
|
+ .pin_config_dbg_show = falcon_pinconf_dbg_show,
|
|
+ .pin_config_group_dbg_show = falcon_pinconf_group_dbg_show,
|
|
+};
|
|
+
|
|
+static struct pinctrl_desc falcon_pctrl_desc = {
|
|
+ .owner = THIS_MODULE,
|
|
+ .pins = falcon_pads,
|
|
+ .confops = &falcon_pinconf_ops,
|
|
+};
|
|
+
|
|
+static inline int falcon_mux_apply(struct pinctrl_dev *pctrldev,
|
|
+ int mfp, int mux)
|
|
+{
|
|
+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
|
|
+ int port = PORT(info->mfp[mfp].pin);
|
|
+
|
|
+ if ((port >= PORTS) || (!info->membase[port]))
|
|
+ return -ENODEV;
|
|
+
|
|
+ pad_w32(info->membase[port], mux,
|
|
+ LTQ_PADC_MUX(PORT_PIN(info->mfp[mfp].pin)));
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct ltq_cfg_param falcon_cfg_params[] = {
|
|
+ {"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
|
|
+ {"lantiq,drive-current", LTQ_PINCONF_PARAM_DRIVE_CURRENT},
|
|
+ {"lantiq,slew-rate", LTQ_PINCONF_PARAM_SLEW_RATE},
|
|
+};
|
|
+
|
|
+static struct ltq_pinmux_info falcon_info = {
|
|
+ .desc = &falcon_pctrl_desc,
|
|
+ .apply_mux = falcon_mux_apply,
|
|
+};
|
|
+
|
|
+
|
|
+
|
|
+
|
|
+/* --------- register the pinctrl layer --------- */
|
|
+
|
|
+int pinctrl_falcon_get_range_size(int id)
|
|
+{
|
|
+ u32 avail;
|
|
+
|
|
+ if ((id >= PORTS) || (!falcon_info.membase[id]))
|
|
+ return -EINVAL;
|
|
+
|
|
+ avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL);
|
|
+
|
|
+ return fls(avail);
|
|
+}
|
|
+
|
|
+void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range)
|
|
+{
|
|
+ pinctrl_add_gpio_range(falcon_info.pctrl, range);
|
|
+}
|
|
+
|
|
+static int pinctrl_falcon_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct device_node *np;
|
|
+ int pad_count = 0;
|
|
+ int ret = 0;
|
|
+
|
|
+ /* load and remap the pad resources of the different banks */
|
|
+ for_each_compatible_node(np, NULL, "lantiq,pad-falcon") {
|
|
+ struct platform_device *ppdev = of_find_device_by_node(np);
|
|
+ const __be32 *bank = of_get_property(np, "lantiq,bank", NULL);
|
|
+ struct resource res;
|
|
+ u32 avail;
|
|
+ int pins;
|
|
+
|
|
+ if (!ppdev) {
|
|
+ dev_err(&pdev->dev, "failed to find pad pdev\n");
|
|
+ continue;
|
|
+ }
|
|
+ if (!bank || *bank >= PORTS)
|
|
+ continue;
|
|
+ if (of_address_to_resource(np, 0, &res))
|
|
+ continue;
|
|
+ falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);
|
|
+ if (IS_ERR(falcon_info.clk[*bank])) {
|
|
+ dev_err(&ppdev->dev, "failed to get clock\n");
|
|
+ return PTR_ERR(falcon_info.clk[*bank]);
|
|
+ }
|
|
+ falcon_info.membase[*bank] =
|
|
+ devm_request_and_ioremap(&pdev->dev, &res);
|
|
+ if (!falcon_info.membase[*bank]) {
|
|
+ dev_err(&pdev->dev,
|
|
+ "Failed to remap memory for bank %d\n",
|
|
+ *bank);
|
|
+ return -ENOMEM;
|
|
+ }
|
|
+ avail = pad_r32(falcon_info.membase[*bank],
|
|
+ LTQ_PADC_AVAIL);
|
|
+ pins = fls(avail);
|
|
+ lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins);
|
|
+ pad_count += pins;
|
|
+ clk_enable(falcon_info.clk[*bank]);
|
|
+ dev_dbg(&pdev->dev, "found %s with %d pads\n",
|
|
+ res.name, pins);
|
|
+ }
|
|
+ dev_dbg(&pdev->dev, "found a total of %d pads\n", pad_count);
|
|
+ falcon_pctrl_desc.name = dev_name(&pdev->dev);
|
|
+ falcon_pctrl_desc.npins = pad_count;
|
|
+
|
|
+ falcon_info.mfp = falcon_mfp;
|
|
+ falcon_info.num_mfp = ARRAY_SIZE(falcon_mfp);
|
|
+ falcon_info.grps = falcon_grps;
|
|
+ falcon_info.num_grps = ARRAY_SIZE(falcon_grps);
|
|
+ falcon_info.funcs = falcon_funcs;
|
|
+ falcon_info.num_funcs = ARRAY_SIZE(falcon_funcs);
|
|
+
|
|
+ ret = ltq_pinctrl_register(pdev, &falcon_info);
|
|
+ if (!ret)
|
|
+ dev_info(&pdev->dev, "Init done\n");
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static const struct of_device_id falcon_match[] = {
|
|
+ { .compatible = "lantiq,pinctrl-falcon" },
|
|
+ {},
|
|
+};
|
|
+MODULE_DEVICE_TABLE(of, falcon_match);
|
|
+
|
|
+static struct platform_driver pinctrl_falcon_driver = {
|
|
+ .probe = pinctrl_falcon_probe,
|
|
+ .driver = {
|
|
+ .name = "pinctrl-falcon",
|
|
+ .owner = THIS_MODULE,
|
|
+ .of_match_table = falcon_match,
|
|
+ },
|
|
+};
|
|
+
|
|
+int __init pinctrl_falcon_init(void)
|
|
+{
|
|
+ return platform_driver_register(&pinctrl_falcon_driver);
|
|
+}
|
|
+
|
|
+core_initcall_sync(pinctrl_falcon_init);
|
|
--
|
|
1.7.10.4
|
|
|