mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-20 11:47:09 +03:00
4f2c17075b
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34061 3c298f89-4303-0410-b956-a3cf2f4a3e73
35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
From c9e854cf940fbc09846c255895efceb3bc9bf095 Mon Sep 17 00:00:00 2001
|
|
From: John Crispin <blogic@openwrt.org>
|
|
Date: Wed, 11 Jul 2012 16:33:43 +0200
|
|
Subject: [PATCH 15/15] GPIO: MIPS: lantiq: fix overflow inside stp-xway
|
|
driver
|
|
|
|
The driver was using a 16 bit field for storing the shadow value of the shift
|
|
register cascade. This resulted in only the first 2 shift registeres receiving
|
|
the correct data. The third shift register would always receive 0x00.
|
|
|
|
Fix this by using a 32bit field for the shadow value.
|
|
|
|
Signed-off-by: John Crispin <blogic@openwrt.org>
|
|
Cc: linux-kernel@vger.kernel.org
|
|
---
|
|
drivers/gpio/gpio-stp-xway.c | 2 +-
|
|
1 file changed, 1 insertion(+), 1 deletion(-)
|
|
|
|
diff --git a/drivers/gpio/gpio-stp-xway.c b/drivers/gpio/gpio-stp-xway.c
|
|
index e35096b..8bead0b 100644
|
|
--- a/drivers/gpio/gpio-stp-xway.c
|
|
+++ b/drivers/gpio/gpio-stp-xway.c
|
|
@@ -82,7 +82,7 @@ struct xway_stp {
|
|
struct gpio_chip gc;
|
|
void __iomem *virt;
|
|
u32 edge; /* rising or falling edge triggered shift register */
|
|
- u16 shadow; /* shadow the shift registers state */
|
|
+ u32 shadow; /* shadow the shift registers state */
|
|
u8 groups; /* we can drive 1-3 groups of 8bit each */
|
|
u8 dsl; /* the 2 LSBs can be driven by the dsl core */
|
|
u8 phy1; /* 3 bits can be driven by phy1 */
|
|
--
|
|
1.7.10.4
|
|
|