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git://projects.qi-hardware.com/openwrt-xburst.git
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git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34061 3c298f89-4303-0410-b956-a3cf2f4a3e73
258 lines
7.4 KiB
Diff
258 lines
7.4 KiB
Diff
From 99f2b107924c07bee0bae7151426495fb815ca6e Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 23 Aug 2012 20:28:32 +0200
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Subject: [PATCH] mtd: lantiq: Add NAND support on Lantiq XWAY SoC.
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The driver uses plat_nand. As the platform_device is loaded from DT, we need
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to lookup the node and attach our xway specific "struct platform_nand_data"
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to it.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
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Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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---
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drivers/mtd/nand/Kconfig | 8 ++
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drivers/mtd/nand/Makefile | 1 +
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drivers/mtd/nand/xway_nand.c | 201 ++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 210 insertions(+)
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create mode 100644 drivers/mtd/nand/xway_nand.c
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diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
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index 7101e8a..ce5cf02 100644
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--- a/drivers/mtd/nand/Kconfig
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+++ b/drivers/mtd/nand/Kconfig
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@@ -580,4 +580,12 @@ config MTD_NAND_FSMC
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Enables support for NAND Flash chips on the ST Microelectronics
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Flexible Static Memory Controller (FSMC)
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+config MTD_NAND_XWAY
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+ tristate "Support for NAND on Lantiq XWAY SoC"
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+ depends on LANTIQ && SOC_TYPE_XWAY
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+ select MTD_NAND_PLATFORM
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+ help
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+ Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
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+ to the External Bus Unit (EBU).
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+
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endif # MTD_NAND
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diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
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index ddee818..c4b0ab3 100644
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--- a/drivers/mtd/nand/Makefile
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+++ b/drivers/mtd/nand/Makefile
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@@ -53,5 +53,6 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o
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obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
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obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
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obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
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+obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
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nand-objs := nand_base.o nand_bbt.o
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diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c
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new file mode 100644
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index 0000000..3f81dc8
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--- /dev/null
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+++ b/drivers/mtd/nand/xway_nand.c
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@@ -0,0 +1,201 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright © 2012 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/mtd/nand.h>
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+#include <linux/of_gpio.h>
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+#include <linux/of_platform.h>
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+
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+#include <lantiq_soc.h>
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+
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+/* nand registers */
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+#define EBU_ADDSEL1 0x24
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+#define EBU_NAND_CON 0xB0
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+#define EBU_NAND_WAIT 0xB4
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+#define EBU_NAND_ECC0 0xB8
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+#define EBU_NAND_ECC_AC 0xBC
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+
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+/* nand commands */
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+#define NAND_CMD_ALE (1 << 2)
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+#define NAND_CMD_CLE (1 << 3)
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+#define NAND_CMD_CS (1 << 4)
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+#define NAND_WRITE_CMD_RESET 0xff
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+#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE)
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+#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE)
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+#define NAND_WRITE_DATA (NAND_CMD_CS)
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+#define NAND_READ_DATA (NAND_CMD_CS)
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+#define NAND_WAIT_WR_C (1 << 3)
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+#define NAND_WAIT_RD (0x1)
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+
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+/* we need to tel the ebu which addr we mapped the nand to */
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+#define ADDSEL1_MASK(x) (x << 4)
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+#define ADDSEL1_REGEN 1
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+
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+/* we need to tell the EBU that we have nand attached and set it up properly */
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+#define BUSCON1_SETUP (1 << 22)
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+#define BUSCON1_BCGEN_RES (0x3 << 12)
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+#define BUSCON1_WAITWRC2 (2 << 8)
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+#define BUSCON1_WAITRDC2 (2 << 6)
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+#define BUSCON1_HOLDC1 (1 << 4)
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+#define BUSCON1_RECOVC1 (1 << 2)
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+#define BUSCON1_CMULT4 1
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+
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+#define NAND_CON_CE (1 << 20)
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+#define NAND_CON_OUT_CS1 (1 << 10)
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+#define NAND_CON_IN_CS1 (1 << 8)
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+#define NAND_CON_PRE_P (1 << 7)
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+#define NAND_CON_WP_P (1 << 6)
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+#define NAND_CON_SE_P (1 << 5)
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+#define NAND_CON_CS_P (1 << 4)
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+#define NAND_CON_CSMUX (1 << 1)
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+#define NAND_CON_NANDM 1
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+
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+static void xway_reset_chip(struct nand_chip *chip)
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+{
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+ unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
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+ unsigned long flags;
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+
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+ nandaddr &= ~NAND_WRITE_ADDR;
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+ nandaddr |= NAND_WRITE_CMD;
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+
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+ /* finish with a reset */
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+ spin_lock_irqsave(&ebu_lock, flags);
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+ writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr);
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+ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
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+ ;
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+ spin_unlock_irqrestore(&ebu_lock, flags);
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+}
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+
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+static void xway_select_chip(struct mtd_info *mtd, int chip)
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+{
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+
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+ switch (chip) {
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+ case -1:
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+ ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
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+ ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
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+ break;
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+ case 0:
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+ ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
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+ ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
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+ break;
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+ default:
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+ BUG();
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+ }
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+}
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+
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+static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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+{
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+ struct nand_chip *this = mtd->priv;
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+ unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
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+ unsigned long flags;
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+
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+ if (ctrl & NAND_CTRL_CHANGE) {
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+ nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR);
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+ if (ctrl & NAND_CLE)
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+ nandaddr |= NAND_WRITE_CMD;
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+ else
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+ nandaddr |= NAND_WRITE_ADDR;
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+ this->IO_ADDR_W = (void __iomem *) nandaddr;
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+ }
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+
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+ if (cmd != NAND_CMD_NONE) {
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+ spin_lock_irqsave(&ebu_lock, flags);
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+ writeb(cmd, this->IO_ADDR_W);
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+ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
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+ ;
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+ spin_unlock_irqrestore(&ebu_lock, flags);
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+ }
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+}
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+
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+static int xway_dev_ready(struct mtd_info *mtd)
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+{
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+ return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD;
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+}
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+
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+static unsigned char xway_read_byte(struct mtd_info *mtd)
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+{
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+ struct nand_chip *this = mtd->priv;
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+ unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
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+ unsigned long flags;
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+ int ret;
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+
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+ spin_lock_irqsave(&ebu_lock, flags);
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+ ret = ltq_r8((void __iomem *)(nandaddr + NAND_READ_DATA));
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+ spin_unlock_irqrestore(&ebu_lock, flags);
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+
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+ return ret;
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+}
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+
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+static int xway_nand_probe(struct platform_device *pdev)
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+{
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+ struct nand_chip *this = platform_get_drvdata(pdev);
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+ unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
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+ const __be32 *cs = of_get_property(pdev->dev.of_node,
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+ "lantiq,cs", NULL);
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+ u32 cs_flag = 0;
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+
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+ /* load our CS from the DT. Either we find a valid 1 or default to 0 */
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+ if (cs && (*cs == 1))
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+ cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
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+
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+ /* setup the EBU to run in NAND mode on our base addr */
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+ ltq_ebu_w32(CPHYSADDR(nandaddr)
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+ | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);
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+
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+ ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
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+ | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
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+ | BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
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+
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+ ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
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+ | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
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+ | cs_flag, EBU_NAND_CON);
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+
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+ /* finish with a reset */
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+ xway_reset_chip(this);
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+
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+ return 0;
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+}
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+
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+/* allow users to override the partition in DT using the cmdline */
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+static const char *part_probes[] = { "cmdlinepart", "ofpart", NULL };
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+
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+static struct platform_nand_data xway_nand_data = {
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+ .chip = {
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+ .nr_chips = 1,
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+ .chip_delay = 30,
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+ .part_probe_types = part_probes,
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+ },
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+ .ctrl = {
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+ .probe = xway_nand_probe,
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+ .cmd_ctrl = xway_cmd_ctrl,
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+ .dev_ready = xway_dev_ready,
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+ .select_chip = xway_select_chip,
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+ .read_byte = xway_read_byte,
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+ }
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+};
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+
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+/*
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+ * Try to find the node inside the DT. If it is available attach out
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+ * platform_nand_data
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+ */
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+static int __init xway_register_nand(void)
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+{
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+ struct device_node *node;
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+ struct platform_device *pdev;
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+
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+ node = of_find_compatible_node(NULL, NULL, "lantiq,nand-xway");
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+ if (!node)
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+ return -ENOENT;
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+ pdev = of_find_device_by_node(node);
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+ if (!pdev)
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+ return -EINVAL;
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+ pdev->dev.platform_data = &xway_nand_data;
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+ of_node_put(node);
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+ return 0;
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+}
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+
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+subsys_initcall(xway_register_nand);
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--
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1.7.10.4
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