mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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4f2c17075b
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34061 3c298f89-4303-0410-b956-a3cf2f4a3e73
211 lines
6.4 KiB
Diff
211 lines
6.4 KiB
Diff
From 4ed46c23c7257e15a419eb3176375601b312c157 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 22 Oct 2012 09:47:09 +0200
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Subject: [PATCH 105/113] MIPS: lantiq: xway: adds reset code for 11G PHYs
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/a | 42 +++++++++++++
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arch/mips/b | 36 +++++++++++
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.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +
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arch/mips/lantiq/xway/reset.c | 63 +++++++++++++++++++-
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4 files changed, 142 insertions(+), 2 deletions(-)
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create mode 100644 arch/mips/a
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create mode 100644 arch/mips/b
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diff --git a/arch/mips/a b/arch/mips/a
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new file mode 100644
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index 0000000..31e61f8
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--- /dev/null
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+++ b/arch/mips/a
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@@ -0,0 +1,42 @@
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+diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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+index 6a2df70..056df1a 100644
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+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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+@@ -87,5 +87,8 @@ extern __iomem void *ltq_cgu_membase;
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+ extern void ltq_pmu_enable(unsigned int module);
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+ extern void ltq_pmu_disable(unsigned int module);
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+
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++/* allow drivers to reset clock domains and ip cores */
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++void ltq_reset_once(unsigned int module, ulong u);
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++
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+ #endif /* CONFIG_SOC_TYPE_XWAY */
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+ #endif /* _LTQ_XWAY_H__ */
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+diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
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+index 22c55f7..c2a7e65 100644
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+--- a/arch/mips/lantiq/xway/reset.c
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++++ b/arch/mips/lantiq/xway/reset.c
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+@@ -55,13 +62,23 @@ unsigned char ltq_boot_select(void)
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+ return (val >> RCU_BOOT_SEL_SHIFT) & RCU_BOOT_SEL_MASK;
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+ }
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+
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++static void ltq_reset_enter(unsigned int module)
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++{
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++ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
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++}
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++
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++static void ltq_reset_leave(unsigned int module)
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++{
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++ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
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++}
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++
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+ /* reset a io domain for u micro seconds */
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+ void ltq_reset_once(unsigned int module, ulong u)
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+ {
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+- ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
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++ ltq_reset_enter(RCU_RST_REQ);
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+ udelay(u);
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+- ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
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++ ltq_reset_leave(RCU_RST_REQ);
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+ }
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+
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+ static void ltq_machine_restart(char *command)
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diff --git a/arch/mips/b b/arch/mips/b
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new file mode 100644
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index 0000000..c6a0323
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--- /dev/null
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+++ b/arch/mips/b
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@@ -0,0 +1,36 @@
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+diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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+index 6a2df70..056df1a 100644
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+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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+@@ -87,8 +87,11 @@ extern __iomem void *ltq_cgu_membase;
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+ extern void ltq_pmu_enable(unsigned int module);
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+ extern void ltq_pmu_disable(unsigned int module);
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+
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++/* allow booting xrx200 phys */
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++int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
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++
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+ #endif /* CONFIG_SOC_TYPE_XWAY */
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+ #endif /* _LTQ_XWAY_H__ */
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+diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
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+index 22c55f7..c2a7e65 100644
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+--- a/arch/mips/lantiq/xway/reset.c
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++++ b/arch/mips/lantiq/xway/reset.c
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+@@ -26,11 +26,18 @@
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+
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+ /* reset request register */
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+ #define RCU_RST_REQ 0x0010
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++
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++#define VR9_RCU_GFS_ADD0 0x0020
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++#define VR9_RCU_GFS_ADD1 0x0068
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++
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+ /* reset status register */
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+ #define RCU_RST_STAT 0x0014
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+
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+ /* reboot bit */
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++#define VR9_RCU_RD_GPHY0 BIT(31)
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+ #define RCU_RD_SRST BIT(30)
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++#define VR9_RCU_RD_GPHY1 BIT(29)
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++
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+ /* reset cause */
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+ #define RCU_STAT_SHIFT 26
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+ /* boot selection */
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diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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index 6b9f5be..056df1a 100644
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--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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@@ -90,5 +90,8 @@ extern void ltq_pmu_disable(unsigned int module);
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/* allow drivers to reset clock domains and ip cores */
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void ltq_reset_once(unsigned int module, ulong u);
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+/* allow booting xrx200 phys */
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+int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
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+
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#endif /* CONFIG_SOC_TYPE_XWAY */
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#endif /* _LTQ_XWAY_H__ */
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diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
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index 1b77f82..56293cf 100644
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--- a/arch/mips/lantiq/xway/reset.c
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+++ b/arch/mips/lantiq/xway/reset.c
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@@ -28,9 +28,15 @@
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#define RCU_RST_REQ 0x0010
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/* reset status register */
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#define RCU_RST_STAT 0x0014
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+/* vr9 gphy registers */
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+#define VR9_RCU_GFS_ADD0 0x0020
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+#define VR9_RCU_GFS_ADD1 0x0068
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/* reboot bit */
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+#define VR9_RCU_RD_GPHY0 BIT(31)
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#define RCU_RD_SRST BIT(30)
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+#define VR9_RCU_RD_GPHY1 BIT(29)
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+
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/* reset cause */
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#define RCU_STAT_SHIFT 26
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/* boot selection */
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@@ -65,13 +71,66 @@ static void ltq_reset_leave(unsigned int module)
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ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
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}
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+/* reset / boot a gphy */
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+static struct ltq_xrx200_gphy_reset {
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+ u32 rd;
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+ u32 addr;
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+} xrx200_gphy[] = {
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+ {VR9_RCU_RD_GPHY0, VR9_RCU_GFS_ADD0},
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+ {VR9_RCU_RD_GPHY1, VR9_RCU_GFS_ADD1},
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+};
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+
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+/* reset and boot a gphy. these phys only exist on xrx200 SoC */
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+int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
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+{
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+ if (id > 1) {
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+ dev_err(dev, "%u is an invalid gphy id\n", id);
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+ return -EINVAL;
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+ }
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+ dev_info(dev, "booting GPHY%u firmware at %X\n", id, dev_addr);
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+
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+ ltq_reset_enter(xrx200_gphy[id].rd);
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+ ltq_rcu_w32(dev_addr, xrx200_gphy[id].addr);
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+ ltq_reset_leave(xrx200_gphy[id].rd);
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(xrx200_gphy_boot);
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+
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/* reset a io domain for u micro seconds */
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void ltq_reset_once(unsigned int module, ulong u)
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{
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- ltq_reset_enter(RCU_RST_REQ);
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+ ltq_reset_enter(module);
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udelay(u);
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- ltq_reset_leave(RCU_RST_REQ);
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+ ltq_reset_leave(module);
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+}
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+
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+int ifx_rcu_rst(unsigned int reset_domain_id, unsigned int module_id)
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+{
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+ ltq_reset_once(BIT(module_id), 20);
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+ return 0;
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+}
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+EXPORT_SYMBOL(ifx_rcu_rst);
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+
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+unsigned int ifx_rcu_rst_req_read(void)
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+{
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+ unsigned int ret;
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+
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+ ret = ltq_rcu_r32(RCU_RST_REQ);
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+
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+ return ret;
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+}
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+EXPORT_SYMBOL(ifx_rcu_rst_req_read);
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+
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+void ifx_rcu_rst_req_write(unsigned int value, unsigned int mask)
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+{
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+ unsigned int ret;
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+
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+ ret = ltq_rcu_r32(RCU_RST_REQ);
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+ ret &= ~mask;
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+ ret |= value & mask;
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+ ltq_rcu_w32(ret, RCU_RST_REQ);
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}
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+EXPORT_SYMBOL(ifx_rcu_rst_req_write);
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static void ltq_machine_restart(char *command)
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{
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--
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1.7.10.4
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