mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-05 20:56:15 +02:00
f49f2aac30
Also override the pll_1000 value. Without these settings ethernet suffers from packet loss. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34316 3c298f89-4303-0410-b956-a3cf2f4a3e73
185 lines
5.0 KiB
Diff
185 lines
5.0 KiB
Diff
--- a/arch/mips/ath79/mach-ap136.c
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+++ b/arch/mips/ath79/mach-ap136.c
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@@ -1,5 +1,5 @@
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/*
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- * Qualcomm Atheros AP136 reference board support
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+ * Atheros AP136 reference board support
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*
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* Copyright (c) 2012 Qualcomm Atheros
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* Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
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@@ -18,23 +18,27 @@
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*
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*/
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-#include <linux/pci.h>
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-#include <linux/ath9k_platform.h>
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+#include <linux/platform_device.h>
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+#include <linux/ar8216_platform.h>
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-#include "machtypes.h"
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+#include <asm/mach-ath79/ar71xx_regs.h>
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+
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+#include "common.h"
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+#include "dev-ap9x-pci.h"
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#include "dev-gpio-buttons.h"
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+#include "dev-eth.h"
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#include "dev-leds-gpio.h"
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-#include "dev-spi.h"
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+#include "dev-m25p80.h"
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#include "dev-usb.h"
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#include "dev-wmac.h"
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-#include "pci.h"
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+#include "machtypes.h"
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-#define AP136_GPIO_LED_STATUS_RED 14
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-#define AP136_GPIO_LED_STATUS_GREEN 19
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#define AP136_GPIO_LED_USB 4
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-#define AP136_GPIO_LED_WLAN_2G 13
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#define AP136_GPIO_LED_WLAN_5G 12
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+#define AP136_GPIO_LED_WLAN_2G 13
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+#define AP136_GPIO_LED_STATUS_RED 14
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#define AP136_GPIO_LED_WPS_RED 15
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+#define AP136_GPIO_LED_STATUS_GREEN 19
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#define AP136_GPIO_LED_WPS_GREEN 20
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#define AP136_GPIO_BTN_WPS 16
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@@ -43,8 +47,10 @@
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#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
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#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
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-#define AP136_WMAC_CALDATA_OFFSET 0x1000
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-#define AP136_PCIE_CALDATA_OFFSET 0x5000
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+#define AP136_MAC0_OFFSET 0
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+#define AP136_MAC1_OFFSET 6
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+#define AP136_WMAC_CALDATA_OFFSET 0x1000
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+#define AP136_PCIE_CALDATA_OFFSET 0x5000
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static struct gpio_led ap136_leds_gpio[] __initdata = {
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{
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@@ -98,63 +104,91 @@ static struct gpio_keys_button ap136_gpi
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},
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};
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-static struct ath79_spi_controller_data ap136_spi0_data = {
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- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
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- .cs_line = 0,
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+static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg = {
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+ .mode = AR8327_PAD_MAC_RGMII,
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+ .txclk_delay_en = true,
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+ .rxclk_delay_en = true,
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+ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
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+ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
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};
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-static struct spi_board_info ap136_spi_info[] = {
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- {
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- .bus_num = 0,
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- .chip_select = 0,
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- .max_speed_hz = 25000000,
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- .modalias = "mx25l6405d",
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- .controller_data = &ap136_spi0_data,
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- }
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+static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg = {
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+ .mode = AR8327_PAD_MAC_SGMII,
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+ .txclk_delay_en = false,
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+ .rxclk_delay_en = true,
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+ .txclk_delay_sel = AR8327_CLK_DELAY_SEL0,
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+ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
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};
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-static struct ath79_spi_platform_data ap136_spi_data = {
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- .bus_num = 0,
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- .num_chipselect = 1,
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+static struct ar8327_platform_data ap136_ar8327_data = {
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+ .pad0_cfg = &ap136_ar8327_pad0_cfg,
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+ .pad6_cfg = &ap136_ar8327_pad6_cfg,
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+ .cpuport_cfg = {
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+ .force_link = 1,
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+ .speed = AR8327_PORT_SPEED_1000,
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+ .duplex = 1,
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+ .txpause = 1,
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+ .rxpause = 1,
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+ }
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};
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-#ifdef CONFIG_PCI
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-static struct ath9k_platform_data ap136_ath9k_data;
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+static struct mdio_board_info ap136_mdio0_info[] = {
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+ {
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+ .bus_id = "ag71xx-mdio.0",
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+ .phy_addr = 0,
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+ .platform_data = &ap136_ar8327_data,
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+ },
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+};
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-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
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+static void __init ap136_gmac_setup(void)
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{
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- if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
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- dev->dev.platform_data = &ap136_ath9k_data;
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+ void __iomem *base;
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+ u32 t;
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- return 0;
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-}
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+ base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
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-static void __init ap136_pci_init(u8 *eeprom)
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-{
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- memcpy(ap136_ath9k_data.eeprom_data, eeprom,
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- sizeof(ap136_ath9k_data.eeprom_data));
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+ t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
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+
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+ t &= ~(QCA955X_ETH_CFG_RGMII_GMAC0 | QCA955X_ETH_CFG_SGMII_GMAC0);
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+ t |= QCA955X_ETH_CFG_RGMII_GMAC0;
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- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
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- ath79_register_pci();
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+ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
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+
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+ iounmap(base);
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}
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-#else
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-static inline void ap136_pci_init(void) {}
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-#endif /* CONFIG_PCI */
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static void __init ap136_setup(void)
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{
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u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
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+ ath79_register_m25p80(NULL);
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+
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ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
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ap136_leds_gpio);
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ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(ap136_gpio_keys),
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ap136_gpio_keys);
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- ath79_register_spi(&ap136_spi_data, ap136_spi_info,
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- ARRAY_SIZE(ap136_spi_info));
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+
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ath79_register_usb();
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- ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
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- ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
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+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
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+ ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
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+
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+ ap136_gmac_setup();
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+
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+ ath79_register_mdio(0, 0x0);
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+
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+ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
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+
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+ mdiobus_register_board_info(ap136_mdio0_info,
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+ ARRAY_SIZE(ap136_mdio0_info));
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+
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+ /* GMAC0 is connected to an AR8327 switch */
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+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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+ ath79_eth0_data.phy_mask = BIT(0);
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+ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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+ ath79_eth0_pll_data.pll_1000 = 0xa6000000;
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+
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+ ath79_register_eth(0);
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}
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MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board",
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