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4f2c17075b
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34061 3c298f89-4303-0410-b956-a3cf2f4a3e73
35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
From c9e854cf940fbc09846c255895efceb3bc9bf095 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 11 Jul 2012 16:33:43 +0200
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Subject: [PATCH 15/15] GPIO: MIPS: lantiq: fix overflow inside stp-xway
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driver
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The driver was using a 16 bit field for storing the shadow value of the shift
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register cascade. This resulted in only the first 2 shift registeres receiving
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the correct data. The third shift register would always receive 0x00.
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Fix this by using a 32bit field for the shadow value.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Cc: linux-kernel@vger.kernel.org
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---
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drivers/gpio/gpio-stp-xway.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/drivers/gpio/gpio-stp-xway.c b/drivers/gpio/gpio-stp-xway.c
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index e35096b..8bead0b 100644
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--- a/drivers/gpio/gpio-stp-xway.c
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+++ b/drivers/gpio/gpio-stp-xway.c
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@@ -82,7 +82,7 @@ struct xway_stp {
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struct gpio_chip gc;
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void __iomem *virt;
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u32 edge; /* rising or falling edge triggered shift register */
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- u16 shadow; /* shadow the shift registers state */
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+ u32 shadow; /* shadow the shift registers state */
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u8 groups; /* we can drive 1-3 groups of 8bit each */
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u8 dsl; /* the 2 LSBs can be driven by the dsl core */
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u8 phy1; /* 3 bits can be driven by phy1 */
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--
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1.7.10.4
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