mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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9def867b97
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19826 3c298f89-4303-0410-b956-a3cf2f4a3e73
159 lines
4.3 KiB
C
159 lines
4.3 KiB
C
/*
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* GPIO support for RDC SoC R3210/R8610
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*
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* Copyright (C) 2007, Florian Fainelli <florian@openwrt.org>
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* Copyright (C) 2008, Volker Weiss <dev@tintuc.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/gpio.h>
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#include <asm/rdc321x_gpio.h>
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#include <asm/rdc321x_defs.h>
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/* spin lock to protect our private copy of GPIO data register plus
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the access to PCI conf registers. */
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static DEFINE_SPINLOCK(gpio_lock);
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/* copy of GPIO data registers */
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static u32 gpio_data_reg1;
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static u32 gpio_data_reg2;
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static inline void rdc321x_conf_write(unsigned addr, u32 value)
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{
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outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR);
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outl(value, RDC3210_CFGREG_DATA);
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}
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static inline void rdc321x_conf_or(unsigned addr, u32 value)
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{
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outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR);
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value |= inl(RDC3210_CFGREG_DATA);
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outl(value, RDC3210_CFGREG_DATA);
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}
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static inline u32 rdc321x_conf_read(unsigned addr)
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{
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outl((1 << 31) | (7 << 11) | addr, RDC3210_CFGREG_ADDR);
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return inl(RDC3210_CFGREG_DATA);
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}
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/* configure pin as GPIO */
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static void rdc321x_configure_gpio(unsigned gpio)
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{
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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rdc321x_conf_or(gpio < 32
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? RDC321X_GPIO_CTRL_REG1 : RDC321X_GPIO_CTRL_REG2,
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1 << (gpio & 0x1f));
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spin_unlock_irqrestore(&gpio_lock, flags);
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}
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/* read GPIO pin */
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static int rdc_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
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{
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u32 reg;
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unsigned long flags;
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spin_lock_irqsave(&gpio_lock, flags);
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reg = rdc321x_conf_read(gpio < 32
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? RDC321X_GPIO_DATA_REG1 : RDC321X_GPIO_DATA_REG2);
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spin_unlock_irqrestore(&gpio_lock, flags);
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return (1 << (gpio & 0x1f)) & reg ? 1 : 0;
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}
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/* set GPIO pin to value */
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static void rdc_gpio_set_value(struct gpio_chip *chip,
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unsigned gpio, int value)
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{
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unsigned long flags;
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u32 reg;
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reg = 1 << (gpio & 0x1f);
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if (gpio < 32) {
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spin_lock_irqsave(&gpio_lock, flags);
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if (value)
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gpio_data_reg1 |= reg;
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else
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gpio_data_reg1 &= ~reg;
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rdc321x_conf_write(RDC321X_GPIO_DATA_REG1, gpio_data_reg1);
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spin_unlock_irqrestore(&gpio_lock, flags);
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} else {
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spin_lock_irqsave(&gpio_lock, flags);
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if (value)
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gpio_data_reg2 |= reg;
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else
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gpio_data_reg2 &= ~reg;
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rdc321x_conf_write(RDC321X_GPIO_DATA_REG2, gpio_data_reg2);
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spin_unlock_irqrestore(&gpio_lock, flags);
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}
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}
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/* configure GPIO pin as input */
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static int rdc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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{
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rdc321x_configure_gpio(gpio);
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return 0;
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}
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/* configure GPIO pin as output and set value */
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static int rdc_gpio_direction_output(struct gpio_chip *chip,
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unsigned gpio, int value)
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{
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rdc321x_configure_gpio(gpio);
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gpio_set_value(gpio, value);
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return 0;
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}
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static struct gpio_chip rdc321x_gpio_chip = {
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.label = "rdc321x-gpio",
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.direction_input = rdc_gpio_direction_input,
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.direction_output = rdc_gpio_direction_output,
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.get = rdc_gpio_get_value,
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.set = rdc_gpio_set_value,
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.base = 0,
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.ngpio = RDC321X_MAX_GPIO,
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};
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/* initially setup the 2 copies of the gpio data registers.
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This function is called before the platform setup code. */
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static int __init rdc321x_gpio_setup(void)
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{
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/* this might not be, what others (BIOS, bootloader, etc.)
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wrote to these registers before, but it's a good guess. Still
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better than just using 0xffffffff. */
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gpio_data_reg1 = rdc321x_conf_read(RDC321X_GPIO_DATA_REG1);
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gpio_data_reg2 = rdc321x_conf_read(RDC321X_GPIO_DATA_REG2);
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printk(KERN_INFO "rdc321x: registering %d GPIOs\n", rdc321x_gpio_chip.ngpio);
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return gpiochip_add(&rdc321x_gpio_chip);
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}
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arch_initcall(rdc321x_gpio_setup);
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