mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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1a29ef8e97
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19815 3c298f89-4303-0410-b956-a3cf2f4a3e73
133 lines
4.1 KiB
C
133 lines
4.1 KiB
C
/*
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* drivers/net/ubi32-eth.h
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* Ubicom32 ethernet TIO interface driver definitions.
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*
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* (C) Copyright 2009, Ubicom, Inc.
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*
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* This file is part of the Ubicom32 Linux Kernel Port.
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*
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* The Ubicom32 Linux Kernel Port is free software: you can redistribute
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* it and/or modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, either version 2 of the
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* License, or (at your option) any later version.
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*
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* The Ubicom32 Linux Kernel Port is distributed in the hope that it
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* will be useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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* the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with the Ubicom32 Linux Kernel Port. If not,
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* see <http://www.gnu.org/licenses/>.
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*
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* Ubicom32 implementation derived from (with many thanks):
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* arch/m68knommu
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* arch/blackfin
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* arch/parisc
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*/
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#ifndef _UBI32_ETH_H
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#define _UBI32_ETH_H
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#include <asm/devtree.h>
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#define UBI32_ETH_NUM_OF_DEVICES 2
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/*
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* Number of bytes trashed beyond the packet data.
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*/
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#define UBI32_ETH_TRASHED_MEMORY (CACHE_LINE_SIZE + ETH_HLEN - 1)
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/*
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* Linux already reserves NET_SKB_PAD bytes of headroom in each sk_buff.
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* We want to be able to reserve at least one cache line to align Ethernet
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* and IP header to cache line.
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* Note that the TIO expects a CACHE_LINE_SIZE - ETH_HLEN aligned Ethernet
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* header, while satisfies NET_IP_ALIGN (= 2) automatically.
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* (NET_SKB_PAD is 16, NET_IP_ALIGN is 2, CACHE_LINE_SIZE is 32).
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* You can add more space by making UBI32_ETH_RESERVE_EXTRA != 0.
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*/
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#define UBI32_ETH_RESERVE_EXTRA (1 * CACHE_LINE_SIZE)
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#define UBI32_ETH_RESERVE_SPACE (UBI32_ETH_RESERVE_EXTRA + CACHE_LINE_SIZE)
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struct ubi32_eth_dma_desc {
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volatile void *data_pointer; /* pointer to the buffer */
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volatile u16 buffer_len; /* the buffer size */
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volatile u16 data_len; /* actual frame length */
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volatile u32 status; /* bit0: status to be update by VP; bit[31:1] time stamp */
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};
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#define TX_DMA_RING_SIZE (1<<8)
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#define TX_DMA_RING_MASK (TX_DMA_RING_SIZE - 1)
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#define RX_DMA_RING_SIZE (1<<8)
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#define RX_DMA_RING_MASK (RX_DMA_RING_SIZE - 1)
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#define RX_DMA_MAX_QUEUE_SIZE (RX_DMA_RING_SIZE - 1) /* no more than (RX_DMA_RING_SIZE - 1) */
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#define RX_MAX_PKT_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN)
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#define RX_MIN_PKT_SIZE ETH_ZLEN
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#define RX_BUF_SIZE (RX_MAX_PKT_SIZE + VLAN_HLEN) /* allow double VLAN tag */
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#define UBI32_ETH_VP_TX_TIMEOUT (10*HZ)
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struct ubi32_eth_vp_stats {
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u32 rx_alloc_err;
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u32 tx_q_full_cnt;
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u32 rx_q_full_cnt;
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u32 rx_throttle;
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};
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struct ubi32_eth_private {
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struct net_device *dev;
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struct ubi32_eth_vp_stats vp_stats;
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spinlock_t lock;
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#ifdef UBICOM32_USE_NAPI
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struct napi_struct napi;
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#else
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struct tasklet_struct tsk;
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#endif
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struct ethtionode *regs;
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u16 rx_tail;
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u16 tx_tail;
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u32 vp_int_bit;
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};
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struct ethtionode {
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struct devtree_node dn;
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volatile u16 command;
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volatile u16 status;
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volatile u16 int_mask; /* interrupt mask */
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volatile u16 int_status; /* interrupt mask */
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volatile u16 tx_in; /* owned by driver */
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volatile u16 tx_out; /* owned by vp */
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volatile u16 rx_in; /* owned by driver */
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volatile u16 rx_out; /* owned by vp */
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u16 tx_sz; /* owned by driver */
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u16 rx_sz; /* owned by driver */
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struct ubi32_eth_dma_desc **tx_dma_ring;
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struct ubi32_eth_dma_desc **rx_dma_ring;
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};
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#define UBI32_ETH_VP_STATUS_LINK (1<<0)
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#define UBI32_ETH_VP_STATUS_SPEED100 (0x1<<1)
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#define UBI32_ETH_VP_STATUS_SPEED1000 (0x1<<2)
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#define UBI32_ETH_VP_STATUS_DUPLEX (0x1<<3)
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#define UBI32_ETH_VP_STATUS_FLOW_CTRL (0x1<<4)
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#define UBI32_ETH_VP_STATUS_RX_STATE (0x1<<5)
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#define UBI32_ETH_VP_STATUS_TX_STATE (0x1<<6)
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#define UBI32_ETH_VP_STATUS_TX_Q_FULL (1<<8)
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#define UBI32_ETH_VP_INT_RX (1<<0)
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#define UBI32_ETH_VP_INT_TX (1<<1)
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#define UBI32_ETH_VP_CMD_RX_ENABLE (1<<0)
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#define UBI32_ETH_VP_CMD_TX_ENABLE (1<<1)
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#define UBI32_ETH_VP_RX_OK (1<<0)
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#define UBI32_ETH_VP_TX_OK (1<<1)
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#define UBI32_TX_BOUND TX_DMA_RING_SIZE
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#define UBI32_RX_BOUND 64
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#define UBI32_ETH_NAPI_WEIGHT 64 /* for GigE */
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#endif
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