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git://projects.qi-hardware.com/openwrt-xburst.git
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7185dc2440
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34687 3c298f89-4303-0410-b956-a3cf2f4a3e73
90 lines
2.8 KiB
Diff
90 lines
2.8 KiB
Diff
From af14a456c58c153c6d761e6c0af48157692b52ad Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 9 Nov 2012 13:43:30 +0100
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Subject: [PATCH 5/6] MIPS: lantiq: adds code for booting GPHY
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The XRX200 family of SoCs has embedded gigabit PHYs. This patch adds code to
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boot them up.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/4522
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---
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.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 ++
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arch/mips/lantiq/xway/reset.c | 36 ++++++++++++++++++++
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2 files changed, 39 insertions(+)
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diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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index 6a2df70..133336b 100644
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--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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@@ -82,6 +82,9 @@ extern __iomem void *ltq_cgu_membase;
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#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
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#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
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+/* allow booting xrx200 phys */
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+int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
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+
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/* request a non-gpio and set the PIO config */
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#define PMU_PPE BIT(13)
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extern void ltq_pmu_enable(unsigned int module);
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diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
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index 2799212..544dbb7 100644
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--- a/arch/mips/lantiq/xway/reset.c
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+++ b/arch/mips/lantiq/xway/reset.c
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@@ -28,9 +28,15 @@
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#define RCU_RST_REQ 0x0010
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/* reset status register */
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#define RCU_RST_STAT 0x0014
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+/* vr9 gphy registers */
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+#define RCU_GFS_ADD0_XRX200 0x0020
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+#define RCU_GFS_ADD1_XRX200 0x0068
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/* reboot bit */
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+#define RCU_RD_GPHY0_XRX200 BIT(31)
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#define RCU_RD_SRST BIT(30)
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+#define RCU_RD_GPHY1_XRX200 BIT(29)
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+
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/* reset cause */
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#define RCU_STAT_SHIFT 26
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/* boot selection */
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@@ -60,6 +66,36 @@ unsigned char ltq_boot_select(void)
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return RCU_BOOT_SEL(val);
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}
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+/* reset / boot a gphy */
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+static struct ltq_xrx200_gphy_reset {
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+ u32 rd;
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+ u32 addr;
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+} xrx200_gphy[] = {
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+ {RCU_RD_GPHY0_XRX200, RCU_GFS_ADD0_XRX200},
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+ {RCU_RD_GPHY1_XRX200, RCU_GFS_ADD1_XRX200},
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+};
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+
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+/* reset and boot a gphy. these phys only exist on xrx200 SoC */
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+int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
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+{
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+ if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) {
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+ dev_err(dev, "this SoC has no GPHY\n");
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+ return -EINVAL;
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+ }
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+ if (id > 1) {
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+ dev_err(dev, "%u is an invalid gphy id\n", id);
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+ return -EINVAL;
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+ }
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+ dev_info(dev, "booting GPHY%u firmware at %X\n", id, dev_addr);
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+
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | xrx200_gphy[id].rd,
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+ RCU_RST_REQ);
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+ ltq_rcu_w32(dev_addr, xrx200_gphy[id].addr);
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~xrx200_gphy[id].rd,
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+ RCU_RST_REQ);
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+ return 0;
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+}
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+
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/* reset a io domain for u micro seconds */
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void ltq_reset_once(unsigned int module, ulong u)
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{
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--
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1.7.10.4
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