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7185dc2440
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34687 3c298f89-4303-0410-b956-a3cf2f4a3e73
48 lines
1.4 KiB
Diff
48 lines
1.4 KiB
Diff
From d8d9b9055d704d6f84ef6346d6826b8a9640f209 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 22 Oct 2012 10:25:39 +0200
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Subject: [PATCH 112/123] MTD: lantiq: xway: fix NAND reset timeout handling
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Fixes a possible deadlock in the code that resets the NAND flash.
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http://lists.infradead.org/pipermail/linux-mtd/2012-September/044240.html
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/mtd/nand/xway_nand.c | 12 ++++++++++--
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1 file changed, 10 insertions(+), 2 deletions(-)
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diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c
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index 3f81dc8..4731300 100644
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--- a/drivers/mtd/nand/xway_nand.c
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+++ b/drivers/mtd/nand/xway_nand.c
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@@ -58,15 +58,23 @@ static void xway_reset_chip(struct nand_chip *chip)
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{
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unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
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unsigned long flags;
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+ unsigned long timeout;
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nandaddr &= ~NAND_WRITE_ADDR;
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nandaddr |= NAND_WRITE_CMD;
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/* finish with a reset */
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+ timeout = jiffies + msecs_to_jiffies(200);
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+
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spin_lock_irqsave(&ebu_lock, flags);
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+
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writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr);
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- while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
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- ;
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+ do {
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+ if ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
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+ break;
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+ cond_resched();
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+ } while (!time_after_eq(jiffies, timeout));
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+
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spin_unlock_irqrestore(&ebu_lock, flags);
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}
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--
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1.7.10.4
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