mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 22:15:30 +02:00
8f313bd0fd
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31902 3c298f89-4303-0410-b956-a3cf2f4a3e73
418 lines
12 KiB
Diff
418 lines
12 KiB
Diff
From d5814bdb661d3dac61422f8f69e459be884c9a9d Mon Sep 17 00:00:00 2001
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From: Maarten ter Huurne <maarten@treewalker.org>
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Date: Tue, 2 Aug 2011 10:49:28 +0200
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Subject: [PATCH 06/21] MTD: NAND: JZ4740: Multi-bank support with
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autodetection
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The platform data can now specify which external memory banks to probe
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for NAND chips, and in which order. Banks that contain a NAND are used
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and the other banks are freed.
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Squashed version of development done in jz-2.6.38 branch.
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Original patch by Lars-Peter Clausen with some bug fixes from me.
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Thanks to Paul Cercueil for the initial autodetection patch.
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---
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arch/mips/include/asm/mach-jz4740/jz4740_nand.h | 4 +
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arch/mips/jz4740/platform.c | 20 ++-
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drivers/mtd/nand/jz4740_nand.c | 228 +++++++++++++++++++----
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3 files changed, 215 insertions(+), 37 deletions(-)
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--- a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
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+++ b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
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@@ -19,6 +19,8 @@
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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+#define JZ_NAND_NUM_BANKS 4
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+
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struct jz_nand_platform_data {
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int num_partitions;
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struct mtd_partition *partitions;
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@@ -27,6 +29,8 @@ struct jz_nand_platform_data {
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unsigned int busy_gpio;
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+ unsigned char banks[JZ_NAND_NUM_BANKS];
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+
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void (*ident_callback)(struct platform_device *, struct nand_chip *,
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struct mtd_partition **, int *num_partitions);
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};
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--- a/arch/mips/jz4740/platform.c
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+++ b/arch/mips/jz4740/platform.c
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@@ -157,11 +157,29 @@ static struct resource jz4740_nand_resou
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.flags = IORESOURCE_MEM,
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},
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{
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- .name = "bank",
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+ .name = "bank1",
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.start = 0x18000000,
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.end = 0x180C0000 - 1,
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.flags = IORESOURCE_MEM,
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},
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+ {
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+ .name = "bank2",
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+ .start = 0x14000000,
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+ .end = 0x140C0000 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .name = "bank3",
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+ .start = 0x0C000000,
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+ .end = 0x0C0C0000 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .name = "bank4",
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+ .start = 0x08000000,
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+ .end = 0x080C0000 - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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};
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struct platform_device jz4740_nand_device = {
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--- a/drivers/mtd/nand/jz4740_nand.c
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+++ b/drivers/mtd/nand/jz4740_nand.c
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@@ -52,9 +52,10 @@
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#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
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#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
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+#define JZ_NAND_CTRL_ASSERT_CHIP_MASK 0xaa
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-#define JZ_NAND_MEM_ADDR_OFFSET 0x10000
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#define JZ_NAND_MEM_CMD_OFFSET 0x08000
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+#define JZ_NAND_MEM_ADDR_OFFSET 0x10000
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struct jz_nand {
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struct mtd_info mtd;
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@@ -62,8 +63,11 @@ struct jz_nand {
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void __iomem *base;
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struct resource *mem;
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- void __iomem *bank_base;
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- struct resource *bank_mem;
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+ unsigned char banks[JZ_NAND_NUM_BANKS];
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+ void __iomem *bank_base[JZ_NAND_NUM_BANKS];
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+ struct resource *bank_mem[JZ_NAND_NUM_BANKS];
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+
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+ int selected_bank;
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struct jz_nand_platform_data *pdata;
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bool is_reading;
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@@ -74,26 +78,50 @@ static inline struct jz_nand *mtd_to_jz_
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return container_of(mtd, struct jz_nand, mtd);
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}
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+static void jz_nand_select_chip(struct mtd_info *mtd, int chipnr)
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+{
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+ struct jz_nand *nand = mtd_to_jz_nand(mtd);
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+ struct nand_chip *chip = mtd->priv;
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+ uint32_t ctrl;
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+ int banknr;
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+
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+ ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
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+ ctrl &= ~JZ_NAND_CTRL_ASSERT_CHIP_MASK;
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+
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+ if (chipnr == -1) {
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+ banknr = -1;
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+ } else {
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+ banknr = nand->banks[chipnr] - 1;
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+ chip->IO_ADDR_R = nand->bank_base[banknr];
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+ chip->IO_ADDR_W = nand->bank_base[banknr];
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+ }
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+ writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
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+
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+ nand->selected_bank = banknr;
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+}
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+
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static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
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{
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struct jz_nand *nand = mtd_to_jz_nand(mtd);
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struct nand_chip *chip = mtd->priv;
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uint32_t reg;
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+ void __iomem *bank_base = nand->bank_base[nand->selected_bank];
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+
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+ BUG_ON(nand->selected_bank < 0);
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if (ctrl & NAND_CTRL_CHANGE) {
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BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
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if (ctrl & NAND_ALE)
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- chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_ADDR_OFFSET;
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+ bank_base += JZ_NAND_MEM_ADDR_OFFSET;
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else if (ctrl & NAND_CLE)
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- chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_CMD_OFFSET;
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- else
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- chip->IO_ADDR_W = nand->bank_base;
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+ bank_base += JZ_NAND_MEM_CMD_OFFSET;
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+ chip->IO_ADDR_W = bank_base;
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reg = readl(nand->base + JZ_REG_NAND_CTRL);
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if (ctrl & NAND_NCE)
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- reg |= JZ_NAND_CTRL_ASSERT_CHIP(0);
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+ reg |= JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
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else
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- reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0);
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+ reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
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writel(reg, nand->base + JZ_REG_NAND_CTRL);
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}
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if (dat != NAND_CMD_NONE)
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@@ -252,7 +280,7 @@ static int jz_nand_correct_ecc_rs(struct
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}
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static int jz_nand_ioremap_resource(struct platform_device *pdev,
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- const char *name, struct resource **res, void __iomem **base)
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+ const char *name, struct resource **res, void *__iomem *base)
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{
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int ret;
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@@ -288,6 +316,90 @@ err:
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return ret;
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}
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+static inline void jz_nand_iounmap_resource(struct resource *res, void __iomem *base)
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+{
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+ iounmap(base);
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+ release_mem_region(res->start, resource_size(res));
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+}
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+
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+static int __devinit jz_nand_detect_bank(struct platform_device *pdev, struct jz_nand *nand, unsigned char bank, size_t chipnr, uint8_t *nand_maf_id, uint8_t *nand_dev_id) {
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+ int ret;
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+ int gpio;
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+ char gpio_name[9];
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+ char res_name[6];
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+ uint32_t ctrl;
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+ struct mtd_info *mtd = &nand->mtd;
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+ struct nand_chip *chip = &nand->chip;
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+
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+ /* Request GPIO port. */
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+ gpio = JZ_GPIO_MEM_CS0 + bank - 1;
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+ sprintf(gpio_name, "NAND CS%d", bank);
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+ ret = gpio_request(gpio, gpio_name);
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+ if (ret) {
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+ dev_warn(&pdev->dev,
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+ "Failed to request %s gpio %d: %d\n",
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+ gpio_name, gpio, ret);
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+ goto notfound_gpio;
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+ }
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+
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+ /* Request I/O resource. */
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+ sprintf(res_name, "bank%d", bank);
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+ ret = jz_nand_ioremap_resource(pdev, res_name,
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+ &nand->bank_mem[bank - 1],
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+ &nand->bank_base[bank - 1]);
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+ if (ret)
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+ goto notfound_resource;
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+
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+ /* Enable chip in bank. */
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+ jz_gpio_set_function(gpio, JZ_GPIO_FUNC_MEM_CS0);
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+ ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
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+ ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1);
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+ writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
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+
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+ if (chipnr == 0) {
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+ /* Detect first chip. */
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+ ret = nand_scan_ident(mtd, 1, NULL);
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+ if (ret)
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+ goto notfound_id;
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+
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+ /* Retrieve the IDs from the first chip. */
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+ chip->select_chip(mtd, 0);
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+ chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
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+ chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
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+ *nand_maf_id = chip->read_byte(mtd);
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+ *nand_dev_id = chip->read_byte(mtd);
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+ } else {
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+ /* Detect additional chip. */
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+ chip->select_chip(mtd, chipnr);
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+ chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
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+ chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
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+ if (*nand_maf_id != chip->read_byte(mtd)
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+ || *nand_dev_id != chip->read_byte(mtd)) {
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+ ret = -ENODEV;
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+ goto notfound_id;
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+ }
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+
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+ /* Update size of the MTD. */
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+ chip->numchips++;
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+ mtd->size += chip->chipsize;
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+ }
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+
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+ dev_info(&pdev->dev, "Found chip %i on bank %i\n", chipnr, bank);
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+ return 0;
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+
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+notfound_id:
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+ dev_info(&pdev->dev, "No chip found on bank %i\n", bank);
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+ ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1));
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+ writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
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+ jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE);
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+ jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
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+ nand->bank_base[bank - 1]);
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+notfound_resource:
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+ gpio_free(gpio);
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+notfound_gpio:
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+ return ret;
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+}
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+
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static int __devinit jz_nand_probe(struct platform_device *pdev)
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{
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int ret;
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@@ -295,6 +407,8 @@ static int __devinit jz_nand_probe(struc
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struct nand_chip *chip;
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struct mtd_info *mtd;
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struct jz_nand_platform_data *pdata = pdev->dev.platform_data;
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+ size_t chipnr, bank_idx;
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+ uint8_t nand_maf_id = 0, nand_dev_id = 0;
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nand = kzalloc(sizeof(*nand), GFP_KERNEL);
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if (!nand) {
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@@ -305,10 +419,6 @@ static int __devinit jz_nand_probe(struc
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ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base);
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if (ret)
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goto err_free;
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- ret = jz_nand_ioremap_resource(pdev, "bank", &nand->bank_mem,
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- &nand->bank_base);
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- if (ret)
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- goto err_iounmap_mmio;
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if (pdata && gpio_is_valid(pdata->busy_gpio)) {
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ret = gpio_request(pdata->busy_gpio, "NAND busy pin");
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@@ -316,7 +426,7 @@ static int __devinit jz_nand_probe(struc
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dev_err(&pdev->dev,
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"Failed to request busy gpio %d: %d\n",
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pdata->busy_gpio, ret);
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- goto err_iounmap_mem;
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+ goto err_iounmap_mmio;
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}
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}
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@@ -338,22 +448,51 @@ static int __devinit jz_nand_probe(struc
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chip->chip_delay = 50;
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chip->cmd_ctrl = jz_nand_cmd_ctrl;
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+ chip->select_chip = jz_nand_select_chip;
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if (pdata && gpio_is_valid(pdata->busy_gpio))
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chip->dev_ready = jz_nand_dev_ready;
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- chip->IO_ADDR_R = nand->bank_base;
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- chip->IO_ADDR_W = nand->bank_base;
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-
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nand->pdata = pdata;
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platform_set_drvdata(pdev, nand);
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- writel(JZ_NAND_CTRL_ENABLE_CHIP(0), nand->base + JZ_REG_NAND_CTRL);
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-
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- ret = nand_scan_ident(mtd, 1, NULL);
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- if (ret) {
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- dev_err(&pdev->dev, "Failed to scan nand\n");
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- goto err_gpio_free;
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+ /* We are going to autodetect NAND chips in the banks specified in the
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+ * platform data. Although nand_scan_ident() can detect multiple chips,
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+ * it requires those chips to be numbered consecuitively, which is not
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+ * always the case for external memory banks. And a fixed chip-to-bank
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+ * mapping is not practical either, since for example Dingoo units
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+ * produced at different times have NAND chips in different banks.
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+ */
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+ chipnr = 0;
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+ for (bank_idx = 0; bank_idx < JZ_NAND_NUM_BANKS; bank_idx++) {
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+ unsigned char bank;
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+
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+ /* If there is no platform data, look for NAND in bank 1,
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+ * which is the most likely bank since it is the only one
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+ * that can be booted from.
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+ */
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+ bank = pdata ? pdata->banks[bank_idx] : bank_idx ^ 1;
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+ if (bank == 0)
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+ break;
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+ if (bank > JZ_NAND_NUM_BANKS) {
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+ dev_warn(&pdev->dev,
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+ "Skipping non-existing bank: %d\n", bank);
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+ continue;
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+ }
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+ /* The detection routine will directly or indirectly call
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+ * jz_nand_select_chip(), so nand->banks has to contain the
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+ * bank we're checking.
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+ */
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+ nand->banks[chipnr] = bank;
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+ if (jz_nand_detect_bank(pdev, nand, bank, chipnr,
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+ &nand_maf_id, &nand_dev_id) == 0)
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+ chipnr++;
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+ else
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+ nand->banks[chipnr] = 0;
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+ }
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+ if (chipnr == 0) {
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+ dev_err(&pdev->dev, "No NAND chips found\n");
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+ goto err_gpio_busy;
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}
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if (pdata && pdata->ident_callback) {
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@@ -363,8 +502,8 @@ static int __devinit jz_nand_probe(struc
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ret = nand_scan_tail(mtd);
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if (ret) {
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- dev_err(&pdev->dev, "Failed to scan nand\n");
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- goto err_gpio_free;
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+ dev_err(&pdev->dev, "Failed to scan NAND\n");
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+ goto err_unclaim_banks;
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}
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ret = mtd_device_parse_register(mtd, NULL, 0,
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@@ -381,14 +520,21 @@ static int __devinit jz_nand_probe(struc
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return 0;
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err_nand_release:
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- nand_release(&nand->mtd);
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-err_gpio_free:
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+ nand_release(mtd);
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+err_unclaim_banks:
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+ while (chipnr--) {
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+ unsigned char bank = nand->banks[chipnr];
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+ gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
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+ jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
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+ nand->bank_base[bank - 1]);
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+ }
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+ writel(0, nand->base + JZ_REG_NAND_CTRL);
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+err_gpio_busy:
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+ if (pdata && gpio_is_valid(pdata->busy_gpio))
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+ gpio_free(pdata->busy_gpio);
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platform_set_drvdata(pdev, NULL);
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- gpio_free(pdata->busy_gpio);
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-err_iounmap_mem:
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- iounmap(nand->bank_base);
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err_iounmap_mmio:
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- iounmap(nand->base);
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+ jz_nand_iounmap_resource(nand->mem, nand->base);
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err_free:
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kfree(nand);
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return ret;
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@@ -397,16 +543,26 @@ err_free:
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static int __devexit jz_nand_remove(struct platform_device *pdev)
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{
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struct jz_nand *nand = platform_get_drvdata(pdev);
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+ struct jz_nand_platform_data *pdata = pdev->dev.platform_data;
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+ size_t i;
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nand_release(&nand->mtd);
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/* Deassert and disable all chips */
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writel(0, nand->base + JZ_REG_NAND_CTRL);
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- iounmap(nand->bank_base);
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- release_mem_region(nand->bank_mem->start, resource_size(nand->bank_mem));
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- iounmap(nand->base);
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- release_mem_region(nand->mem->start, resource_size(nand->mem));
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+ for (i = 0; i < JZ_NAND_NUM_BANKS; ++i) {
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+ unsigned char bank = nand->banks[i];
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+ if (bank != 0) {
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+ jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
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+ nand->bank_base[bank - 1]);
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+ gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
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+ }
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+ }
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+ if (pdata && gpio_is_valid(pdata->busy_gpio))
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+ gpio_free(pdata->busy_gpio);
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+
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+ jz_nand_iounmap_resource(nand->mem, nand->base);
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platform_set_drvdata(pdev, NULL);
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kfree(nand);
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