mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-29 01:14:39 +02:00
d9cf9b6852
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@9757 3c298f89-4303-0410-b956-a3cf2f4a3e73
361 lines
10 KiB
C
361 lines
10 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2006 infineon
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/version.h>
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#include <linux/types.h>
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#include <linux/fs.h>
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#include <linux/miscdevice.h>
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#include <linux/init.h>
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#include <asm/uaccess.h>
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#include <asm/unistd.h>
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#include <linux/errno.h>
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#include <asm/danube/danube.h>
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#include <asm/danube/danube_gpio.h>
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#define LED_CONFIG 0x01
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#define CONFIG_OPERATION_UPDATE_SOURCE 0x0001
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#define CONFIG_OPERATION_BLINK 0x0002
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#define CONFIG_OPERATION_UPDATE_CLOCK 0x0004
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#define CONFIG_OPERATION_STORE_MODE 0x0008
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#define CONFIG_OPERATION_SHIFT_CLOCK 0x0010
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#define CONFIG_OPERATION_DATA_OFFSET 0x0020
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#define CONFIG_OPERATION_NUMBER_OF_LED 0x0040
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#define CONFIG_OPERATION_DATA 0x0080
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#define CONFIG_OPERATION_MIPS0_ACCESS 0x0100
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#define CONFIG_DATA_CLOCK_EDGE 0x0200
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#define DANUBE_LED_CLK_EDGE DANUBE_LED_FALLING
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//#define DANUBE_LED_CLK_EDGE DANUBE_LED_RISING
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#define LED_SH_PORT 0
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#define LED_SH_PIN 4
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#define LED_SH_DIR 1
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#define LED_SH_ALTSEL0 1
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#define LED_SH_ALTSEL1 0
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#define LED_SH_OPENDRAIN 1
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#define LED_D_PORT 0
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#define LED_D_PIN 5
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#define LED_D_DIR 1
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#define LED_D_ALTSEL0 1
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#define LED_D_ALTSEL1 0
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#define LED_D_OPENDRAIN 1
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#define LED_ST_PORT 0
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#define LED_ST_PIN 6
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#define LED_ST_DIR 1
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#define LED_ST_ALTSEL0 1
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#define LED_ST_ALTSEL1 0
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#define LED_ST_OPENDRAIN 1
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#define LED_ADSL0_PORT 0
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#define LED_ADSL0_PIN 4
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#define LED_ADSL0_DIR 1
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#define LED_ADSL0_ALTSEL0 0
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#define LED_ADSL0_ALTSEL1 1
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#define LED_ADSL0_OPENDRAIN 1
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#define LED_ADSL1_PORT 0
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#define LED_ADSL1_PIN 5
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#define LED_ADSL1_DIR 1
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#define LED_ADSL1_ALTSEL0 1
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#define LED_ADSL1_ALTSEL1 1
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#define LED_ADSL1_OPENDRAIN 1
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#if (LED_SH_PORT == LED_ADSL0_PORT && LED_SH_PIN == LED_ADSL0_PIN) \
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|| (LED_D_PORT == LED_ADSL0_PORT && LED_D_PIN == LED_ADSL0_PIN) \
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|| (LED_ST_PORT == LED_ADSL0_PORT && LED_ST_PIN == LED_ADSL0_PIN) \
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|| (LED_SH_PORT == LED_ADSL1_PORT && LED_SH_PIN == LED_ADSL1_PIN) \
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|| (LED_D_PORT == LED_ADSL1_PORT && LED_D_PIN == LED_ADSL1_PIN) \
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|| (LED_ST_PORT == LED_ADSL1_PORT && LED_ST_PIN == LED_ADSL1_PIN)
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#define ADSL_LED_IS_EXCLUSIVE 1
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#else
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#define ADSL_LED_IS_EXCLUSIVE 0
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#endif
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#if LED_SH_DIR
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#define LED_SH_DIR_SETUP danube_port_set_dir_out
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#else
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#define LED_SH_DIR_SETUP danube_port_clear_dir_out
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#endif
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#if LED_SH_ALTSEL0
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#define LED_SH_ALTSEL0_SETUP danube_port_set_altsel0
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#else
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#define LED_SH_ALTSEL0_SETUP danube_port_clear_altsel0
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#endif
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#if LED_SH_ALTSEL1
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#define LED_SH_ALTSEL1_SETUP danube_port_set_altsel1
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#else
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#define LED_SH_ALTSEL1_SETUP danube_port_clear_altsel1
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#endif
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#if LED_SH_OPENDRAIN
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#define LED_SH_OPENDRAIN_SETUP danube_port_set_open_drain
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#else
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#define LED_SH_OPENDRAIN_SETUP danube_port_clear_open_drain
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#endif
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#if LED_D_DIR
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#define LED_D_DIR_SETUP danube_port_set_dir_out
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#else
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#define LED_D_DIR_SETUP danube_port_clear_dir_out
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#endif
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#if LED_D_ALTSEL0
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#define LED_D_ALTSEL0_SETUP danube_port_set_altsel0
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#else
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#define LED_D_ALTSEL0_SETUP danube_port_clear_altsel0
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#endif
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#if LED_D_ALTSEL1
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#define LED_D_ALTSEL1_SETUP danube_port_set_altsel1
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#else
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#define LED_D_ALTSEL1_SETUP danube_port_clear_altsel1
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#endif
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#if LED_D_OPENDRAIN
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#define LED_D_OPENDRAIN_SETUP danube_port_set_open_drain
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#else
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#define LED_D_OPENDRAIN_SETUP danube_port_clear_open_drain
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#endif
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#if LED_ST_DIR
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#define LED_ST_DIR_SETUP danube_port_set_dir_out
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#else
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#define LED_ST_DIR_SETUP danube_port_clear_dir_out
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#endif
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#if LED_ST_ALTSEL0
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#define LED_ST_ALTSEL0_SETUP danube_port_set_altsel0
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#else
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#define LED_ST_ALTSEL0_SETUP danube_port_clear_altsel0
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#endif
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#if LED_ST_ALTSEL1
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#define LED_ST_ALTSEL1_SETUP danube_port_set_altsel1
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#else
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#define LED_ST_ALTSEL1_SETUP danube_port_clear_altsel1
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#endif
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#if LED_ST_OPENDRAIN
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#define LED_ST_OPENDRAIN_SETUP danube_port_set_open_drain
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#else
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#define LED_ST_OPENDRAIN_SETUP danube_port_clear_open_drain
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#endif
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#if LED_ADSL0_DIR
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#define LED_ADSL0_DIR_SETUP danube_port_set_dir_out
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#else
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#define LED_ADSL0_DIR_SETUP danube_port_clear_dir_out
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#endif
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#if LED_ADSL0_ALTSEL0
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#define LED_ADSL0_ALTSEL0_SETUP danube_port_set_altsel0
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#else
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#define LED_ADSL0_ALTSEL0_SETUP danube_port_clear_altsel0
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#endif
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#if LED_ADSL0_ALTSEL1
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#define LED_ADSL0_ALTSEL1_SETUP danube_port_set_altsel1
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#else
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#define LED_ADSL0_ALTSEL1_SETUP danube_port_clear_altsel1
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#endif
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#if LED_ADSL0_OPENDRAIN
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#define LED_ADSL0_OPENDRAIN_SETUP danube_port_set_open_drain
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#else
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#define LED_ADSL0_OPENDRAIN_SETUP danube_port_clear_open_drain
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#endif
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#if LED_ADSL1_DIR
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#define LED_ADSL1_DIR_SETUP danube_port_set_dir_out
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#else
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#define LED_ADSL1_DIR_SETUP danube_port_clear_dir_out
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#endif
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#if LED_ADSL1_ALTSEL0
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#define LED_ADSL1_ALTSEL0_SETUP danube_port_set_altsel0
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#else
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#define LED_ADSL1_ALTSEL0_SETUP danube_port_clear_altsel0
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#endif
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#if LED_ADSL1_ALTSEL1
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#define LED_ADSL1_ALTSEL1_SETUP danube_port_set_altsel1
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#else
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#define LED_ADSL1_ALTSEL1_SETUP danube_port_clear_altsel1
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#endif
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#if LED_ADSL1_OPENDRAIN
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#define LED_ADSL1_OPENDRAIN_SETUP danube_port_set_open_drain
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#else
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#define LED_ADSL1_OPENDRAIN_SETUP danube_port_clear_open_drain
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#endif
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#define SET_BITS(x, msb, lsb, value) (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
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static int danube_led_major;
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static int
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danube_led_setup_gpio (void)
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{
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/*
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* Set LED_ST
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* I don't check the return value, because I'm sure the value is valid
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* and the pins are reserved already.
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*/
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LED_ST_ALTSEL0_SETUP(LED_ST_PORT, LED_ST_PIN);
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LED_ST_ALTSEL1_SETUP(LED_ST_PORT, LED_ST_PIN);
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LED_ST_DIR_SETUP(LED_ST_PORT, LED_ST_PIN);
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LED_ST_OPENDRAIN_SETUP(LED_ST_PORT, LED_ST_PIN);
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/*
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* Set LED_D
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*/
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LED_D_ALTSEL0_SETUP(LED_D_PORT, LED_D_PIN);
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LED_D_ALTSEL1_SETUP(LED_D_PORT, LED_D_PIN);
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LED_D_DIR_SETUP(LED_D_PORT, LED_D_PIN);
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LED_D_OPENDRAIN_SETUP(LED_D_PORT, LED_D_PIN);
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/*
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* Set LED_SH
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*/
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LED_SH_ALTSEL0_SETUP(LED_SH_PORT, LED_SH_PIN);
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LED_SH_ALTSEL1_SETUP(LED_SH_PORT, LED_SH_PIN);
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LED_SH_DIR_SETUP(LED_SH_PORT, LED_SH_PIN);
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LED_SH_OPENDRAIN_SETUP(LED_SH_PORT, LED_SH_PIN);
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return 0;
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}
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static void
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danube_led_enable (void)
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{
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int err = 1000000;
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writel(readl(DANUBE_PMU_PWDCR) & ~DANUBE_PMU_PWDCR_LED, DANUBE_PMU_PWDCR);
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while (--err && (readl(DANUBE_PMU_PWDSR) & DANUBE_PMU_PWDCR_LED)) {}
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if (!err)
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panic("Activating LED in PMU failed!");
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}
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static inline void
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danube_led_disable (void)
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{
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writel(readl(DANUBE_PMU_PWDCR) | DANUBE_PMU_PWDCR_LED, DANUBE_PMU_PWDCR);
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}
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static int
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led_ioctl (struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
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{
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int ret = -EINVAL;
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switch ( cmd )
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{
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case LED_CONFIG:
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break;
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}
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return ret;
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}
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static int
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led_open (struct inode *inode, struct file *file)
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{
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return 0;
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}
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static int
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led_release (struct inode *inode, struct file *file)
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{
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return 0;
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}
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static struct file_operations danube_led_fops = {
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.owner = THIS_MODULE,
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.ioctl = led_ioctl,
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.open = led_open,
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.release = led_release
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};
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/*
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Map for LED on reference board
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WLAN_READ LED11 OUT1 15
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WARNING LED12 OUT2 14
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FXS1_LINK LED13 OUT3 13
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FXS2_LINK LED14 OUT4 12
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FXO_ACT LED15 OUT5 11
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USB_LINK LED16 OUT6 10
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ADSL2_LINK LED19 OUT7 9
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BT_LINK LED17 OUT8 8
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SD_LINK LED20 OUT9 7
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ADSL2_TRAFFIC LED31 OUT16 0
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Map for hardware relay on reference board
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USB Power On OUT11 5
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RELAY OUT12 4
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*/
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int __init
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danube_led_init (void)
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{
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int ret = 0;
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danube_led_setup_gpio();
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writel(0, DANUBE_LED_AR);
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writel(0xff00, DANUBE_LED_CPU0);
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writel(0, DANUBE_LED_CPU1);
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writel(0x8000ffff, DANUBE_LED_CON0);
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/* setup the clock edge that the shift register is triggered on */
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writel(readl(DANUBE_LED_CON0) & ~DANUBE_LED_EDGE_MASK, DANUBE_LED_CON0);
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writel(readl(DANUBE_LED_CON0) | DANUBE_LED_CLK_EDGE, DANUBE_LED_CON0);
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/* per default leds 15-0 are set */
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writel(DANUBE_LED_GROUP1 | DANUBE_LED_GROUP0, DANUBE_LED_CON1);
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/* leds are update periodically by the FPID */
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writel(readl(DANUBE_LED_CON1) & ~DANUBE_LED_UPD_MASK, DANUBE_LED_CON1);
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writel(readl(DANUBE_LED_CON1) | DANUBE_LED_UPD_SRC_FPI, DANUBE_LED_CON1);
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/* set led update speed */
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writel(readl(DANUBE_LED_CON1) & ~DANUBE_LED_MASK, DANUBE_LED_CON1);
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writel(readl(DANUBE_LED_CON1) | DANUBE_LED_8HZ, DANUBE_LED_CON1);
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/* adsl 0 and 1 leds are updated by the arc */
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writel(readl(DANUBE_LED_CON0) | DANUBE_LED_ADSL_SRC, DANUBE_LED_CON0);
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/* per default, the leds are turned on */
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danube_led_enable();
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danube_led_major = register_chrdev(0, "danube_led", &danube_led_fops);
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if (!danube_led_major)
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{
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printk("danube_led: Error! Could not register device. %d\n", danube_led_major);
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ret = -EINVAL;
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goto out;
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}
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printk(KERN_INFO "danube_led : device registered on major %d\n", danube_led_major);
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out:
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return ret;
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}
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void __exit
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danube_led_exit (void)
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{
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unregister_chrdev(danube_led_major, "danube_led");
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}
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module_init(danube_led_init);
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module_exit(danube_led_exit);
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