mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-24 13:41:32 +02:00
bf183aeff8
* this adds sflash support for ssb devices * the flash is now a platform device * minor updates git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27902 3c298f89-4303-0410-b956-a3cf2f4a3e73
396 lines
10 KiB
Diff
396 lines
10 KiB
Diff
From 1ba12ca9e05153fbc611918ec0ea4cd9ec97f2c8 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Wed, 22 Jun 2011 22:16:35 +0200
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Subject: [PATCH 09/26] bcm47xx: make it possible to build bcm47xx without ssb.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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arch/mips/Kconfig | 8 +-------
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arch/mips/bcm47xx/Kconfig | 18 ++++++++++++++++++
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arch/mips/bcm47xx/Makefile | 3 ++-
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arch/mips/bcm47xx/gpio.c | 6 ++++++
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arch/mips/bcm47xx/nvram.c | 4 ++++
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arch/mips/bcm47xx/serial.c | 4 ++++
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arch/mips/bcm47xx/setup.c | 8 ++++++++
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arch/mips/bcm47xx/time.c | 2 ++
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arch/mips/include/asm/mach-bcm47xx/bcm47xx.h | 4 ++++
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arch/mips/include/asm/mach-bcm47xx/gpio.h | 12 ++++++++++++
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arch/mips/pci/pci-bcm47xx.c | 6 ++++++
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drivers/watchdog/bcm47xx_wdt.c | 4 ++++
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12 files changed, 71 insertions(+), 8 deletions(-)
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create mode 100644 arch/mips/bcm47xx/Kconfig
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -91,15 +91,8 @@ config BCM47XX
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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select IRQ_CPU
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- select SYS_HAS_CPU_MIPS32_R1
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_LITTLE_ENDIAN
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- select SSB
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- select SSB_DRIVER_MIPS
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- select SSB_DRIVER_EXTIF
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- select SSB_EMBEDDED
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- select SSB_B43_PCI_BRIDGE if PCI
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- select SSB_PCICORE_HOSTMODE if PCI
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select GENERIC_GPIO
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select SYS_HAS_EARLY_PRINTK
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select CFE
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@@ -785,6 +778,7 @@ endchoice
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source "arch/mips/alchemy/Kconfig"
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source "arch/mips/ath79/Kconfig"
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+source "arch/mips/bcm47xx/Kconfig"
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source "arch/mips/bcm63xx/Kconfig"
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source "arch/mips/jazz/Kconfig"
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source "arch/mips/jz4740/Kconfig"
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--- /dev/null
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+++ b/arch/mips/bcm47xx/Kconfig
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@@ -0,0 +1,18 @@
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+if BCM47XX
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+
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+config BCM47XX_SSB
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+ bool "SSB Support for Broadcom BCM47XX"
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select SSB
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+ select SSB_DRIVER_MIPS
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+ select SSB_DRIVER_EXTIF
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+ select SSB_EMBEDDED
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+ select SSB_B43_PCI_BRIDGE if PCI
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+ select SSB_PCICORE_HOSTMODE if PCI
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+ default y
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+ help
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+ Add support for old Broadcom BCM47xx boards with Sonics Silicon Backplane support.
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+
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+ This will generate an image with support for SSB and MIPS32 R1 instruction set.
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+
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+endif
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--- a/arch/mips/bcm47xx/Makefile
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+++ b/arch/mips/bcm47xx/Makefile
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@@ -3,4 +3,5 @@
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# under Linux.
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#
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-obj-y := gpio.o irq.o nvram.o prom.o serial.o setup.o time.o wgt634u.o
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+obj-y += gpio.o irq.o nvram.o prom.o serial.o setup.o time.o
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+obj-$(CONFIG_BCM47XX_SSB) += wgt634u.o
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--- a/arch/mips/bcm47xx/gpio.c
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+++ b/arch/mips/bcm47xx/gpio.c
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@@ -21,6 +21,7 @@ static DECLARE_BITMAP(gpio_in_use, BCM47
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int gpio_request(unsigned gpio, const char *tag)
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{
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switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) &&
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((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES))
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@@ -34,6 +35,7 @@ int gpio_request(unsigned gpio, const ch
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return -EBUSY;
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return 0;
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+#endif
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}
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return -EINVAL;
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}
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@@ -42,6 +44,7 @@ EXPORT_SYMBOL(gpio_request);
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void gpio_free(unsigned gpio)
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{
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switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco) &&
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((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES))
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@@ -53,6 +56,7 @@ void gpio_free(unsigned gpio)
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clear_bit(gpio, gpio_in_use);
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return;
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+#endif
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}
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}
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EXPORT_SYMBOL(gpio_free);
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@@ -60,6 +64,7 @@ EXPORT_SYMBOL(gpio_free);
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int gpio_to_irq(unsigned gpio)
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{
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switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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if (ssb_chipco_available(&bcm47xx_bus.ssb.chipco))
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return ssb_mips_irq(bcm47xx_bus.ssb.chipco.dev) + 2;
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@@ -67,6 +72,7 @@ int gpio_to_irq(unsigned gpio)
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return ssb_mips_irq(bcm47xx_bus.ssb.extif.dev) + 2;
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else
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return -EINVAL;
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+#endif
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}
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return -EINVAL;
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}
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--- a/arch/mips/bcm47xx/nvram.c
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+++ b/arch/mips/bcm47xx/nvram.c
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@@ -26,7 +26,9 @@ static char nvram_buf[NVRAM_SPACE];
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/* Probe for NVRAM header */
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static void early_nvram_init(void)
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{
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+#ifdef CONFIG_BCM47XX_SSB
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struct ssb_mipscore *mcore_ssb;
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+#endif
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struct nvram_header *header;
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int i;
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u32 base = 0;
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@@ -35,11 +37,13 @@ static void early_nvram_init(void)
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u32 *src, *dst;
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switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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mcore_ssb = &bcm47xx_bus.ssb.mipscore;
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base = mcore_ssb->flash_window;
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lim = mcore_ssb->flash_window_size;
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break;
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+#endif
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}
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off = FLASH_MIN;
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--- a/arch/mips/bcm47xx/serial.c
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+++ b/arch/mips/bcm47xx/serial.c
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@@ -23,6 +23,7 @@ static struct platform_device uart8250_d
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},
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};
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+#ifdef CONFIG_BCM47XX_SSB
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static int __init uart8250_init_ssb(void)
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{
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int i;
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@@ -44,12 +45,15 @@ static int __init uart8250_init_ssb(void
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}
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return platform_device_register(&uart8250_device);
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}
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+#endif
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static int __init uart8250_init(void)
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{
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switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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return uart8250_init_ssb();
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+#endif
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}
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return -EINVAL;
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}
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--- a/arch/mips/bcm47xx/setup.c
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+++ b/arch/mips/bcm47xx/setup.c
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@@ -47,9 +47,11 @@ static void bcm47xx_machine_restart(char
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local_irq_disable();
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/* Set the watchdog timer to reset immediately */
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switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1);
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break;
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+#endif
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}
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while (1)
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cpu_relax();
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@@ -60,14 +62,17 @@ static void bcm47xx_machine_halt(void)
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/* Disable interrupts and watchdog and spin forever */
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local_irq_disable();
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switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0);
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break;
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+#endif
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}
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while (1)
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cpu_relax();
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}
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+#ifdef CONFIG_BCM47XX_SSB
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#define READ_FROM_NVRAM(_outvar, name, buf) \
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if (nvram_getprefix(prefix, name, buf, sizeof(buf)) >= 0)\
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sprom->_outvar = simple_strtoul(buf, NULL, 0);
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@@ -288,13 +293,16 @@ static void __init bcm47xx_register_ssb(
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}
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}
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}
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+#endif
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void __init plat_mem_setup(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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+#ifdef CONFIG_BCM47XX_SSB
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bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB;
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bcm47xx_register_ssb();
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+#endif
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_machine_restart = bcm47xx_machine_restart;
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_machine_halt = bcm47xx_machine_halt;
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--- a/arch/mips/bcm47xx/time.c
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+++ b/arch/mips/bcm47xx/time.c
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@@ -40,9 +40,11 @@ void __init plat_time_init(void)
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write_c0_compare(0xffff);
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switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
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break;
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+#endif
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}
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if (!hz)
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--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
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+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
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@@ -22,11 +22,15 @@
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#include <linux/ssb/ssb.h>
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enum bcm47xx_bus_type {
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+#ifdef CONFIG_BCM47XX_SSB
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BCM47XX_BUS_TYPE_SSB,
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+#endif
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};
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union bcm47xx_bus {
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+#ifdef CONFIG_BCM47XX_SSB
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struct ssb_bus ssb;
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+#endif
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};
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extern union bcm47xx_bus bcm47xx_bus;
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--- a/arch/mips/include/asm/mach-bcm47xx/gpio.h
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+++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
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@@ -22,8 +22,10 @@ extern int gpio_to_irq(unsigned gpio);
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static inline int gpio_get_value(unsigned gpio)
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{
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switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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return ssb_gpio_in(&bcm47xx_bus.ssb, 1 << gpio);
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+#endif
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}
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return -EINVAL;
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}
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@@ -31,18 +33,22 @@ static inline int gpio_get_value(unsigne
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static inline void gpio_set_value(unsigned gpio, int value)
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{
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switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio,
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value ? 1 << gpio : 0);
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+#endif
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}
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}
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static inline int gpio_direction_input(unsigned gpio)
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{
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switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 0);
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return 0;
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+#endif
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}
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return -EINVAL;
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}
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@@ -50,6 +56,7 @@ static inline int gpio_direction_input(u
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static inline int gpio_direction_output(unsigned gpio, int value)
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{
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switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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/* first set the gpio out value */
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ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio,
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@@ -57,6 +64,7 @@ static inline int gpio_direction_output(
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/* then set the gpio mode */
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ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 1 << gpio);
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return 0;
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+#endif
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}
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return -EINVAL;
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}
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@@ -64,10 +72,12 @@ static inline int gpio_direction_output(
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static inline int gpio_intmask(unsigned gpio, int value)
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{
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switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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ssb_gpio_intmask(&bcm47xx_bus.ssb, 1 << gpio,
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value ? 1 << gpio : 0);
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return 0;
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+#endif
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}
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return -EINVAL;
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}
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@@ -75,10 +85,12 @@ static inline int gpio_intmask(unsigned
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static inline int gpio_polarity(unsigned gpio, int value)
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{
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switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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ssb_gpio_polarity(&bcm47xx_bus.ssb, 1 << gpio,
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value ? 1 << gpio : 0);
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return 0;
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+#endif
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}
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return -EINVAL;
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}
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--- a/arch/mips/pci/pci-bcm47xx.c
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+++ b/arch/mips/pci/pci-bcm47xx.c
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@@ -25,6 +25,7 @@
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/ssb/ssb.h>
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+#include <bcm47xx.h>
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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@@ -33,9 +34,13 @@ int __init pcibios_map_irq(const struct
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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+#ifdef CONFIG_BCM47XX_SSB
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int res;
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u8 slot, pin;
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+ if (bcm47xx_bus_type != BCM47XX_BUS_TYPE_SSB)
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+ return 0;
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+
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res = ssb_pcibios_plat_dev_init(dev);
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if (res < 0) {
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printk(KERN_ALERT "PCI: Failed to init device %s\n",
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@@ -55,5 +60,6 @@ int pcibios_plat_dev_init(struct pci_dev
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}
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dev->irq = res;
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+#endif
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return 0;
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}
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--- a/drivers/watchdog/bcm47xx_wdt.c
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+++ b/drivers/watchdog/bcm47xx_wdt.c
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@@ -55,17 +55,21 @@ static inline void bcm47xx_wdt_hw_start(
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{
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/* this is 2,5s on 100Mhz clock and 2s on 133 Mhz */
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switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0xfffffff);
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break;
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+#endif
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}
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}
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static inline int bcm47xx_wdt_hw_stop(void)
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{
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switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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case BCM47XX_BUS_TYPE_SSB:
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return ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0);
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+#endif
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}
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return -EINVAL;
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}
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