mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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1a29ef8e97
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19815 3c298f89-4303-0410-b956-a3cf2f4a3e73
321 lines
6.6 KiB
C
321 lines
6.6 KiB
C
/*
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* arch/ubicom32/include/asm/thread.h
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* Ubicom32 architecture specific thread definitions.
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*
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* (C) Copyright 2009, Ubicom, Inc.
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*
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* This file is part of the Ubicom32 Linux Kernel Port.
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*
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* The Ubicom32 Linux Kernel Port is free software: you can redistribute
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* it and/or modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, either version 2 of the
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* License, or (at your option) any later version.
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*
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* The Ubicom32 Linux Kernel Port is distributed in the hope that it
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* will be useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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* the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with the Ubicom32 Linux Kernel Port. If not,
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* see <http://www.gnu.org/licenses/>.
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*
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* Ubicom32 implementation derived from (with many thanks):
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* arch/m68knommu
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* arch/blackfin
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* arch/parisc
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*/
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#ifndef _ASM_UBICOM32_THREAD_H
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#define _ASM_UBICOM32_THREAD_H
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#if !defined(__ASSEMBLY__)
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#include <asm/ptrace.h>
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#include <asm/ubicom32-common.h>
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typedef int thread_t;
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typedef unsigned char thread_type_t;
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typedef void (*thread_exec_fn_t)(void *arg);
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#define THREAD_NULL 0x40
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#define THREAD_TYPE_HRT (1 << 0)
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#define THREAD_TYPE_SPECIAL 0
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#define THREAD_TYPE_NORMAL 0
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#define THREAD_TYPE_BACKGROUND (1 << 1)
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/*
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* This is the upper bound on the maximum hardware threads that one will find
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* on a Ubicom processor. It is used to size per hardware thread data structures.
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*/
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#define THREAD_ARCHITECTURAL_MAX 16
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/*
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* TODO: Rename this at some point to be thread_
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*/
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extern unsigned int sw_ksp[THREAD_ARCHITECTURAL_MAX];
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/*
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* thread_get_self()
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*/
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static inline thread_t thread_get_self(void)
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{
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thread_t result;
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/*
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* Note that ROSR has zeroes in bits 6 through 31 and so we don't need
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* to do any additional bit masking here.
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*/
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asm (
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"lsr.4 %0, ROSR, #2 \n\t"
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: "=d" (result)
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:
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: "cc"
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);
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return result;
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}
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/*
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* thread_suspend()
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*/
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static inline void thread_suspend(void)
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{
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asm volatile (
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"suspend\n\t"
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:
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:
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);
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}
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/*
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* thread_resume()
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*/
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static inline void thread_resume(thread_t thread)
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{
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asm volatile (
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"move.4 MT_ACTIVE_SET, %0 \n\t"
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"pipe_flush 0 \n\t"
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"pipe_flush 0 \n\t"
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:
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: "d" (1 << thread)
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);
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}
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/*
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* thread_enable_mask()
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* Enable all threads in the mask.
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*
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* All writes to MT_EN must be protected by the MT_EN_LOCK bit
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*/
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static inline void thread_enable_mask(unsigned int mask)
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{
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/*
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* must flush the pipeline twice.
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* first pipe_flush is to ensure write to MT_EN is completed
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* second one is to ensure any new instructions from
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* the targeted thread (the one being disabled), that
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* are issued while the write to MT_EN is being executed,
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* are completed.
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*/
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UBICOM32_LOCK(MT_EN_LOCK_BIT);
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asm volatile (
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"or.4 MT_EN, MT_EN, %0 \n\t"
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"pipe_flush 0 \n\t"
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"pipe_flush 0 \n\t"
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:
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: "d" (mask)
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: "cc"
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);
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UBICOM32_UNLOCK(MT_EN_LOCK_BIT);
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}
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/*
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* thread_enable()
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*/
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static inline void thread_enable(thread_t thread)
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{
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thread_enable_mask(1 << thread);
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}
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/*
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* thread_disable_mask()
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* Disable all threads in the mask.
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*
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* All writes to MT_EN must be protected by the MT_EN_LOCK bit
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*/
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static inline void thread_disable_mask(unsigned int mask)
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{
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/*
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* must flush the pipeline twice.
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* first pipe_flush is to ensure write to MT_EN is completed
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* second one is to ensure any new instructions from
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* the targeted thread (the one being disabled), that
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* are issued while the write to MT_EN is being executed,
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* are completed.
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*/
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UBICOM32_LOCK(MT_EN_LOCK_BIT);
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asm volatile (
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"and.4 MT_EN, MT_EN, %0 \n\t"
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"pipe_flush 0 \n\t"
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"pipe_flush 0 \n\t"
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:
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: "d" (~mask)
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: "cc"
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);
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UBICOM32_UNLOCK(MT_EN_LOCK_BIT);
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}
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/*
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* thread_disable()
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*/
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static inline void thread_disable(thread_t thread)
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{
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thread_disable_mask(1 << thread);
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}
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/*
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* thread_disable_others()
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* Disable all other threads
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*/
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static inline void thread_disable_others(void)
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{
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thread_t self = thread_get_self();
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thread_disable_mask(~(1 << self));
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}
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/*
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* thread_is_trapped()
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* Is the specified tid trapped?
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*/
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static inline int thread_is_trapped(thread_t tid)
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{
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int thread_mask = (1 << tid);
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int trap_thread;
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asm (
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"move.4 %0, MT_TRAP \n\t"
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: "=d" (trap_thread)
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:
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);
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return (trap_thread & thread_mask);
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}
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/*
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* thread_is_enabled()
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* Is the specified tid enabled?
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*/
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static inline int thread_is_enabled(thread_t tid)
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{
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int thread_mask = (1 << tid);
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int enabled_threads;
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asm (
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"move.4 %0, MT_EN \n\t"
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: "=d" (enabled_threads)
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:
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);
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return (enabled_threads & thread_mask);
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}
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/*
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* thread_get_instruction_count()
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*/
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static inline unsigned int thread_get_instruction_count(void)
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{
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unsigned int result;
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asm (
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"move.4 %0, INST_CNT \n\t"
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: "=r" (result)
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);
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return result;
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}
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/*
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* thread_get_pc()
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* pc could point to a speculative and cancelled instruction unless thread is disabled
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*/
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static inline void *thread_get_pc(thread_t thread)
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{
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void *result;
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asm (
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"move.4 csr, %1 \n\t"
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"setcsr_flush 0 \n\t"
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"move.4 %0, pc \n\t"
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"move.4 csr, #0 \n\t"
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"setcsr_flush 0 \n\t"
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: "=r" (result)
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: "r" ((thread << 9) | (1 << 8))
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);
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return result;
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}
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/*
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* thread_get_trap_cause()
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* This should be called only when the thread is not running
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*/
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static inline unsigned int thread_get_trap_cause(thread_t thread)
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{
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unsigned int result;
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asm (
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"move.4 csr, %1 \n\t"
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"setcsr_flush 0 \n\t"
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"move.4 %0, trap_cause \n\t"
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"move.4 csr, #0 \n\t"
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"setcsr_flush 0 \n\t"
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: "=r" (result)
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: "r" ((thread << 9) | (1 << 8))
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);
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return result;
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}
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/*
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* THREAD_STALL macro.
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*/
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#define THREAD_STALL \
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asm volatile ( \
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"move.4 mt_dbg_active_clr, #-1 \n\t" \
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"pipe_flush 0 \n\t" \
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: \
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: \
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)
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extern unsigned int thread_get_mainline(void);
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extern void thread_set_mainline(thread_t tid);
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extern thread_t thread_alloc(void);
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extern thread_t thread_start(thread_t thread, thread_exec_fn_t exec, void *arg, unsigned int *sp_high, thread_type_t type);
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/*
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* asm macros
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*/
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asm (
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/*
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* thread_get_self
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* Read and shift the current thread into reg
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*
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* Note that we don't need to mask the result as bits 6 through 31 of the
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* ROSR are zeroes.
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*/
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".macro thread_get_self reg \n\t"
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" lsr.4 \\reg, ROSR, #2 \n\t"
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".endm \n\t"
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/*
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* thread_get_self_mask
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* Read and shift the current thread mask into reg
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*/
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".macro thread_get_self_mask reg \n\t"
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" lsr.4 \\reg, ROSR, #2 \n\t"
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" lsl.4 \\reg, #1, \\reg \n\t" /* Thread bit */
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".endm \n\t"
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);
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#else /* __ASSEMBLY__ */
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#include <asm/thread-asm.h>
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_UBICOM32_THREAD_H */
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