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The nand subtarget is not working yet. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@33983 3c298f89-4303-0410-b956-a3cf2f4a3e73
240 lines
6.9 KiB
Diff
240 lines
6.9 KiB
Diff
From 5d0de52f8e36916485a61b820916b71b5d918e6f Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Sun, 24 Jun 2012 13:44:23 +0200
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Subject: [PATCH 19/34] MIPS: ath79: add IRQ handling code for the QCA955X SoCs
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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arch/mips/ath79/irq.c | 110 ++++++++++++++++++++++--
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 32 +++++++
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arch/mips/include/asm/mach-ath79/irq.h | 9 ++-
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3 files changed, 142 insertions(+), 9 deletions(-)
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--- a/arch/mips/ath79/irq.c
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+++ b/arch/mips/ath79/irq.c
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@@ -130,7 +130,10 @@ static void __init ath79_misc_irq_init(v
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if (soc_is_ar71xx() || soc_is_ar913x())
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ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
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- else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x())
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+ else if (soc_is_ar724x() ||
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+ soc_is_ar933x() ||
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+ soc_is_ar934x() ||
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+ soc_is_qca955x())
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ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
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else
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BUG();
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@@ -177,6 +180,88 @@ static void ar934x_ip2_irq_init(void)
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irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
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}
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+static void qca955x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
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+{
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+ u32 status;
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+
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+ disable_irq_nosync(irq);
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+
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+ status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
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+ status &= QCA955X_EXT_INT_PCIE_RC1_ALL | QCA955X_EXT_INT_WMAC_ALL;
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+
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+ if (status == 0) {
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+ spurious_interrupt();
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+ goto enable;
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+ }
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+
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+ if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) {
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+ /* TODO: flush DDR? */
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+ generic_handle_irq(ATH79_IP2_IRQ(0));
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+ }
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+
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+ if (status & QCA955X_EXT_INT_WMAC_ALL) {
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+ /* TODO: flsuh DDR? */
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+ generic_handle_irq(ATH79_IP2_IRQ(1));
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+ }
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+
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+enable:
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+ enable_irq(irq);
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+}
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+
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+static void qca955x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
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+{
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+ u32 status;
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+
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+ disable_irq_nosync(irq);
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+
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+ status = ath79_reset_rr(QCA955X_RESET_REG_EXT_INT_STATUS);
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+ status &= QCA955X_EXT_INT_PCIE_RC2_ALL |
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+ QCA955X_EXT_INT_USB1 |
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+ QCA955X_EXT_INT_USB2;
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+
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+ if (status == 0) {
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+ spurious_interrupt();
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+ goto enable;
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+ }
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+
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+ if (status & QCA955X_EXT_INT_USB1) {
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+ /* TODO: flush DDR? */
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+ generic_handle_irq(ATH79_IP3_IRQ(0));
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+ }
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+
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+ if (status & QCA955X_EXT_INT_USB2) {
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+ /* TODO: flsuh DDR? */
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+ generic_handle_irq(ATH79_IP3_IRQ(1));
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+ }
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+
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+ if (status & QCA955X_EXT_INT_PCIE_RC2_ALL) {
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+ /* TODO: flush DDR? */
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+ generic_handle_irq(ATH79_IP3_IRQ(2));
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+ }
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+
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+enable:
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+ enable_irq(irq);
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+}
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+
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+static void qca955x_irq_init(void)
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+{
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+ int i;
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+
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+ for (i = ATH79_IP2_IRQ_BASE;
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+ i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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+ irq_set_chip_and_handler(i, &dummy_irq_chip,
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+ handle_level_irq);
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+
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+ irq_set_chained_handler(ATH79_CPU_IRQ_IP2, qca955x_ip2_irq_dispatch);
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+
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+ for (i = ATH79_IP3_IRQ_BASE;
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+ i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
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+ irq_set_chip_and_handler(i, &dummy_irq_chip,
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+ handle_level_irq);
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+
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+ irq_set_chained_handler(ATH79_CPU_IRQ_IP3, qca955x_ip3_irq_dispatch);
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+}
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+
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned long pending;
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@@ -212,6 +297,17 @@ asmlinkage void plat_irq_dispatch(void)
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* Issue a flush in the handlers to ensure that the driver sees
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* the update.
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*/
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+
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+static void ath79_default_ip2_handler(void)
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+{
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+ do_IRQ(ATH79_CPU_IRQ_IP2);
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+}
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+
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+static void ath79_default_ip3_handler(void)
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+{
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+ do_IRQ(ATH79_CPU_IRQ_USB);
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+}
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+
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static void ar71xx_ip2_handler(void)
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{
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ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
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@@ -236,11 +332,6 @@ static void ar933x_ip2_handler(void)
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do_IRQ(ATH79_CPU_IRQ_IP2);
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}
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-static void ar934x_ip2_handler(void)
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-{
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- do_IRQ(ATH79_CPU_IRQ_IP2);
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-}
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-
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static void ar71xx_ip3_handler(void)
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{
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ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
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@@ -286,8 +377,11 @@ void __init arch_init_irq(void)
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ath79_ip2_handler = ar933x_ip2_handler;
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ath79_ip3_handler = ar933x_ip3_handler;
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} else if (soc_is_ar934x()) {
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- ath79_ip2_handler = ar934x_ip2_handler;
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+ ath79_ip2_handler = ath79_default_ip2_handler;
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ath79_ip3_handler = ar934x_ip3_handler;
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+ } else if (soc_is_qca955x()) {
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+ ath79_ip2_handler = ath79_default_ip2_handler;
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+ ath79_ip3_handler = ath79_default_ip3_handler;
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} else {
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BUG();
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}
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@@ -298,4 +392,6 @@ void __init arch_init_irq(void)
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if (soc_is_ar934x())
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ar934x_ip2_irq_init();
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+ else if (soc_is_qca955x())
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+ qca955x_irq_init();
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}
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -300,6 +300,7 @@
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#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
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#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
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+#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
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#define MISC_INT_ETHSW BIT(12)
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#define MISC_INT_TIMER4 BIT(10)
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@@ -398,6 +399,37 @@
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AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
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AR934X_PCIE_WMAC_INT_PCIE_RC3)
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+#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
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+#define QCA955X_EXT_INT_WMAC_TX BIT(1)
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+#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
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+#define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
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+#define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
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+#define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
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+#define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
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+#define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
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+#define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
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+#define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
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+#define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
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+#define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
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+#define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
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+#define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
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+#define QCA955X_EXT_INT_USB1 BIT(24)
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+#define QCA955X_EXT_INT_USB2 BIT(28)
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+
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+#define QCA955X_EXT_INT_WMAC_ALL \
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+ (QCA955X_EXT_INT_WMAC_MISC | QCA955X_EXT_INT_WMAC_TX | \
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+ QCA955X_EXT_INT_WMAC_RXLP | QCA955X_EXT_INT_WMAC_RXHP)
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+
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+#define QCA955X_EXT_INT_PCIE_RC1_ALL \
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+ (QCA955X_EXT_INT_PCIE_RC1 | QCA955X_EXT_INT_PCIE_RC1_INT0 | \
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+ QCA955X_EXT_INT_PCIE_RC1_INT1 | QCA955X_EXT_INT_PCIE_RC1_INT2 | \
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+ QCA955X_EXT_INT_PCIE_RC1_INT3)
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+
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+#define QCA955X_EXT_INT_PCIE_RC2_ALL \
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+ (QCA955X_EXT_INT_PCIE_RC2 | QCA955X_EXT_INT_PCIE_RC2_INT0 | \
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+ QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
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+ QCA955X_EXT_INT_PCIE_RC2_INT3)
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+
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#define REV_ID_MAJOR_MASK 0xfff0
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#define REV_ID_MAJOR_AR71XX 0x00a0
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#define REV_ID_MAJOR_AR913X 0x00b0
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--- a/arch/mips/include/asm/mach-ath79/irq.h
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+++ b/arch/mips/include/asm/mach-ath79/irq.h
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@@ -10,7 +10,7 @@
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#define __ASM_MACH_ATH79_IRQ_H
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#define MIPS_CPU_IRQ_BASE 0
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-#define NR_IRQS 48
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+#define NR_IRQS 51
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#define ATH79_MISC_IRQ_BASE 8
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#define ATH79_MISC_IRQ_COUNT 32
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@@ -23,8 +23,13 @@
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#define ATH79_IP2_IRQ_COUNT 2
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#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x))
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+#define ATH79_IP3_IRQ_BASE (ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT)
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+#define ATH79_IP3_IRQ_COUNT 3
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+#define ATH79_IP3_IRQ(_x) (ATH79_IP3_IRQ_BASE + (_x))
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+
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#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
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-#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
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+#define ATH79_CPU_IRQ_IP3 (MIPS_CPU_IRQ_BASE + 3)
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+#define ATH79_CPU_IRQ_USB ATH79_CPU_IRQ_IP3
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#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
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#define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5)
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#define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6)
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