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git://projects.qi-hardware.com/openwrt-xburst.git
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9a462204d1
This watchdog driver should work with SoC having a PMU. This fixes #11720. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34323 3c298f89-4303-0410-b956-a3cf2f4a3e73
55 lines
1.4 KiB
Diff
55 lines
1.4 KiB
Diff
--- a/drivers/ssb/driver_chipcommon.c
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+++ b/drivers/ssb/driver_chipcommon.c
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@@ -288,6 +288,24 @@ static u32 ssb_chipco_alp_clock(struct s
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return 20000000;
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}
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+static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
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+{
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+ u32 nb;
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+
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+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
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+ if (cc->dev->id.revision < 26)
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+ nb = 16;
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+ else
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+ nb = (cc->dev->id.revision >= 37) ? 32 : 24;
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+ } else {
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+ nb = 28;
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+ }
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+ if (nb == 32)
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+ return 0xffffffff;
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+ else
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+ return (1 << nb) - 1;
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+}
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+
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void ssb_chipcommon_init(struct ssb_chipcommon *cc)
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{
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if (!cc->dev)
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@@ -405,8 +423,24 @@ void ssb_chipco_timing_init(struct ssb_c
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/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
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void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
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{
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- /* instant NMI */
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- chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
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+ u32 maxt;
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+ enum ssb_clkmode clkmode;
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+
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+ maxt = ssb_chipco_watchdog_get_max_timer(cc);
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+ if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
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+ if (ticks == 1)
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+ ticks = 2;
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+ else if (ticks > maxt)
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+ ticks = maxt;
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+ chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
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+ } else {
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+ clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
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+ ssb_chipco_set_clockmode(cc, clkmode);
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+ if (ticks > maxt)
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+ ticks = maxt;
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+ /* instant NMI */
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+ chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
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+ }
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}
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void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
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