mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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8f09b983e5
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29125 3c298f89-4303-0410-b956-a3cf2f4a3e73
288 lines
6.7 KiB
C
288 lines
6.7 KiB
C
/*
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* Atheros AR7XXX/AR9XXX SoC GPIO API support
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*
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/gpio.h>
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#include <asm/mach-ar71xx/ar71xx.h>
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static DEFINE_SPINLOCK(ar71xx_gpio_lock);
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unsigned long ar71xx_gpio_count;
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EXPORT_SYMBOL(ar71xx_gpio_count);
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void __ar71xx_gpio_set_value(unsigned gpio, int value)
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{
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void __iomem *base = ar71xx_gpio_base;
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if (value)
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__raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET);
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else
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__raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR);
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}
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EXPORT_SYMBOL(__ar71xx_gpio_set_value);
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int __ar71xx_gpio_get_value(unsigned gpio)
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{
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return (__raw_readl(ar71xx_gpio_base + AR71XX_GPIO_REG_IN) >> gpio) & 1;
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}
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EXPORT_SYMBOL(__ar71xx_gpio_get_value);
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static int ar71xx_gpio_get_value(struct gpio_chip *chip, unsigned offset)
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{
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return __ar71xx_gpio_get_value(offset);
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}
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static void ar71xx_gpio_set_value(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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__ar71xx_gpio_set_value(offset, value);
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}
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static int ar71xx_gpio_direction_input(struct gpio_chip *chip,
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unsigned offset)
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{
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void __iomem *base = ar71xx_gpio_base;
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unsigned long flags;
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spin_lock_irqsave(&ar71xx_gpio_lock, flags);
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__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
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base + AR71XX_GPIO_REG_OE);
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spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
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return 0;
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}
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static int ar71xx_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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void __iomem *base = ar71xx_gpio_base;
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unsigned long flags;
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spin_lock_irqsave(&ar71xx_gpio_lock, flags);
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if (value)
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__raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
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else
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__raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
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__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
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base + AR71XX_GPIO_REG_OE);
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spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
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return 0;
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}
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static int ar934x_gpio_direction_input(struct gpio_chip *chip,
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unsigned offset)
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{
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void __iomem *base = ar71xx_gpio_base;
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unsigned long flags;
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spin_lock_irqsave(&ar71xx_gpio_lock, flags);
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__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset),
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base + AR71XX_GPIO_REG_OE);
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spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
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return 0;
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}
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static int ar934x_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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void __iomem *base = ar71xx_gpio_base;
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unsigned long flags;
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spin_lock_irqsave(&ar71xx_gpio_lock, flags);
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if (value)
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__raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET);
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else
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__raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR);
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__raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset),
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base + AR71XX_GPIO_REG_OE);
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spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
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return 0;
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}
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static struct gpio_chip ar71xx_gpio_chip = {
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.label = "ar71xx",
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.get = ar71xx_gpio_get_value,
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.set = ar71xx_gpio_set_value,
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.direction_input = ar71xx_gpio_direction_input,
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.direction_output = ar71xx_gpio_direction_output,
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.base = 0,
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.ngpio = AR71XX_GPIO_COUNT,
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};
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void ar71xx_gpio_function_enable(u32 mask)
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{
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void __iomem *base = ar71xx_gpio_base;
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unsigned long flags;
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unsigned int reg;
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if (ar71xx_soc == AR71XX_SOC_AR9341 ||
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ar71xx_soc == AR71XX_SOC_AR9342 ||
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ar71xx_soc == AR71XX_SOC_AR9344) {
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reg = AR934X_GPIO_REG_FUNC;
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} else {
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reg = AR71XX_GPIO_REG_FUNC;
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}
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spin_lock_irqsave(&ar71xx_gpio_lock, flags);
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__raw_writel(__raw_readl(base + reg) | mask, base + reg);
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/* flush write */
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(void) __raw_readl(base + reg);
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spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
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}
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void ar71xx_gpio_function_disable(u32 mask)
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{
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void __iomem *base = ar71xx_gpio_base;
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unsigned long flags;
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unsigned int reg;
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if (ar71xx_soc == AR71XX_SOC_AR9341 ||
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ar71xx_soc == AR71XX_SOC_AR9342 ||
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ar71xx_soc == AR71XX_SOC_AR9344) {
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reg = AR934X_GPIO_REG_FUNC;
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} else {
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reg = AR71XX_GPIO_REG_FUNC;
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}
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spin_lock_irqsave(&ar71xx_gpio_lock, flags);
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__raw_writel(__raw_readl(base + reg) & ~mask, base + reg);
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/* flush write */
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(void) __raw_readl(base + reg);
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spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
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}
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void ar71xx_gpio_function_setup(u32 set, u32 clear)
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{
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void __iomem *base = ar71xx_gpio_base;
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unsigned long flags;
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unsigned int reg;
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if (ar71xx_soc == AR71XX_SOC_AR9341 ||
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ar71xx_soc == AR71XX_SOC_AR9342 ||
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ar71xx_soc == AR71XX_SOC_AR9344) {
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reg = AR934X_GPIO_REG_FUNC;
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} else {
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reg = AR71XX_GPIO_REG_FUNC;
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}
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spin_lock_irqsave(&ar71xx_gpio_lock, flags);
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__raw_writel((__raw_readl(base + reg) & ~clear) | set, base + reg);
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/* flush write */
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(void) __raw_readl(base + reg);
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spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
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}
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EXPORT_SYMBOL(ar71xx_gpio_function_setup);
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void __init ar71xx_gpio_output_select(unsigned gpio, u8 val)
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{
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void __iomem *base = ar71xx_gpio_base;
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unsigned long flags;
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unsigned int reg;
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u32 t, s;
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if (ar71xx_soc != AR71XX_SOC_AR9341 &&
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ar71xx_soc != AR71XX_SOC_AR9342 &&
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ar71xx_soc != AR71XX_SOC_AR9344)
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return;
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if (gpio >= AR934X_GPIO_COUNT)
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return;
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reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
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s = 8 * (gpio % 4);
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spin_lock_irqsave(&ar71xx_gpio_lock, flags);
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t = __raw_readl(base + reg);
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t &= ~(0xff << s);
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t |= val << s;
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__raw_writel(t, base + reg);
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/* flush write */
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(void) __raw_readl(base + reg);
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spin_unlock_irqrestore(&ar71xx_gpio_lock, flags);
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}
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void __init ar71xx_gpio_init(void)
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{
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int err;
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if (!request_mem_region(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
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"AR71xx GPIO controller"))
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panic("cannot allocate AR71xx GPIO registers page");
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switch (ar71xx_soc) {
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case AR71XX_SOC_AR7130:
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case AR71XX_SOC_AR7141:
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case AR71XX_SOC_AR7161:
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ar71xx_gpio_chip.ngpio = AR71XX_GPIO_COUNT;
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break;
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case AR71XX_SOC_AR7240:
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case AR71XX_SOC_AR7241:
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case AR71XX_SOC_AR7242:
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ar71xx_gpio_chip.ngpio = AR724X_GPIO_COUNT;
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break;
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case AR71XX_SOC_AR9130:
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case AR71XX_SOC_AR9132:
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ar71xx_gpio_chip.ngpio = AR91XX_GPIO_COUNT;
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break;
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case AR71XX_SOC_AR9330:
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case AR71XX_SOC_AR9331:
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ar71xx_gpio_chip.ngpio = AR933X_GPIO_COUNT;
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break;
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case AR71XX_SOC_AR9341:
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case AR71XX_SOC_AR9342:
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case AR71XX_SOC_AR9344:
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ar71xx_gpio_chip.ngpio = AR934X_GPIO_COUNT;
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ar71xx_gpio_chip.direction_input = ar934x_gpio_direction_input;
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ar71xx_gpio_chip.direction_output = ar934x_gpio_direction_output;
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break;
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default:
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BUG();
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}
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err = gpiochip_add(&ar71xx_gpio_chip);
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if (err)
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panic("cannot add AR71xx GPIO chip, error=%d", err);
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}
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