mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-18 23:47:31 +02:00
95ef6e1d42
Thank you Peter Wagner for the patch. I refreshed the kernel patches and added the md5sum of the kernel. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@26905 3c298f89-4303-0410-b956-a3cf2f4a3e73
137 lines
5.3 KiB
Diff
137 lines
5.3 KiB
Diff
--- a/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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@@ -1192,10 +1192,10 @@ void ssb_device_enable(struct ssb_device
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}
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EXPORT_SYMBOL(ssb_device_enable);
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-/* Wait for a bit in a register to get set or unset.
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+/* Wait for bitmask in a register to get set or cleared.
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* timeout is in units of ten-microseconds */
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-static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
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- int timeout, int set)
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+static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
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+ int timeout, int set)
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{
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int i;
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u32 val;
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@@ -1203,7 +1203,7 @@ static int ssb_wait_bit(struct ssb_devic
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for (i = 0; i < timeout; i++) {
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val = ssb_read32(dev, reg);
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if (set) {
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- if (val & bitmask)
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+ if ((val & bitmask) == bitmask)
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return 0;
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} else {
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if (!(val & bitmask))
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@@ -1220,20 +1220,38 @@ static int ssb_wait_bit(struct ssb_devic
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void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
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{
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- u32 reject;
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+ u32 reject, val;
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if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
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return;
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reject = ssb_tmslow_reject_bitmask(dev);
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- ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
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- ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
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- ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
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- ssb_write32(dev, SSB_TMSLOW,
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- SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
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- reject | SSB_TMSLOW_RESET |
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- core_specific_flags);
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- ssb_flush_tmslow(dev);
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+
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+ if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
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+ ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
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+ ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
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+ ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
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+
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+ if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
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+ val = ssb_read32(dev, SSB_IMSTATE);
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+ val |= SSB_IMSTATE_REJECT;
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+ ssb_write32(dev, SSB_IMSTATE, val);
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+ ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
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+ 0);
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+ }
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+
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+ ssb_write32(dev, SSB_TMSLOW,
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+ SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
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+ reject | SSB_TMSLOW_RESET |
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+ core_specific_flags);
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+ ssb_flush_tmslow(dev);
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+
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+ if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
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+ val = ssb_read32(dev, SSB_IMSTATE);
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+ val &= ~SSB_IMSTATE_REJECT;
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+ ssb_write32(dev, SSB_IMSTATE, val);
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+ }
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+ }
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ssb_write32(dev, SSB_TMSLOW,
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reject | SSB_TMSLOW_RESET |
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--- a/drivers/ssb/pci.c
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+++ b/drivers/ssb/pci.c
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@@ -468,10 +468,14 @@ static void sprom_extract_r45(struct ssb
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SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
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SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
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SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
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+ SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
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+ SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
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} else {
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SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
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SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
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SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
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+ SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
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+ SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
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}
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SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
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SSB_SPROM4_ANTAVAIL_A_SHIFT);
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@@ -641,7 +645,7 @@ static int sprom_extract(struct ssb_bus
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break;
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default:
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ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
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- " revision %d detected. Will extract"
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+ " revision %d detected. Will extract"
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" v1\n", out->revision);
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out->revision = 1;
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sprom_extract_r123(out, in);
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--- a/include/linux/ssb/ssb_regs.h
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+++ b/include/linux/ssb/ssb_regs.h
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@@ -85,6 +85,8 @@
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#define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
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#define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
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#define SSB_IMSTATE_TO 0x00040000 /* Timeout */
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+#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
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+#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
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#define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
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#define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
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#define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
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@@ -97,7 +99,6 @@
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#define SSB_TMSLOW_RESET 0x00000001 /* Reset */
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#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
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#define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
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-#define SSB_TMSLOW_PHYCLK 0x00000010 /* MAC PHY Clock Control Enable */
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#define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
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#define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
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#define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */
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@@ -268,6 +269,8 @@
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/* SPROM Revision 4 */
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#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
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#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
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+#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
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+#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
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#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
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#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
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#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
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@@ -358,6 +361,8 @@
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#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
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#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
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#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
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+#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
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+#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
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#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
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#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
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#define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
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