mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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60da4b4a94
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17440 3c298f89-4303-0410-b956-a3cf2f4a3e73
99 lines
2.3 KiB
C
99 lines
2.3 KiB
C
/*
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* Ralink SoC Interrupt controller routines
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*
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* Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/bitops.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-ralink/common.h>
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/* INTC register offsets */
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#define INTC_REG_STATUS0 0x00
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#define INTC_REG_STATUS1 0x04
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#define INTC_REG_TYPE 0x20
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#define INTC_REG_RAW_STATUS 0x30
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#define INTC_REG_ENABLE 0x34
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#define INTC_REG_DISABLE 0x38
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#define INTC_INT_GLOBAL BIT(31)
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#define INTC_IRQ_COUNT 32
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static unsigned int ramips_intc_irq_base;
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static void __iomem *ramips_intc_base;
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static inline void ramips_intc_wr(u32 val, unsigned reg)
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{
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__raw_writel(val, ramips_intc_base + reg);
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}
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static inline u32 ramips_intc_rr(unsigned reg)
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{
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return __raw_readl(ramips_intc_base + reg);
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}
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static void ramips_intc_irq_unmask(unsigned int irq)
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{
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irq -= ramips_intc_irq_base;
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ramips_intc_wr((1 << irq), INTC_REG_ENABLE);
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}
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static void ramips_intc_irq_mask(unsigned int irq)
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{
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irq -= ramips_intc_irq_base;
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ramips_intc_wr((1 << irq), INTC_REG_DISABLE);
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}
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static struct irq_chip ramips_intc_irq_chip = {
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.name = "INTC",
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.unmask = ramips_intc_irq_unmask,
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.mask = ramips_intc_irq_mask,
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.mask_ack = ramips_intc_irq_mask,
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};
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static struct irqaction ramips_intc_irqaction = {
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.handler = no_action,
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.name = "cascade [INTC]",
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};
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void __init ramips_intc_irq_init(unsigned intc_base, unsigned irq,
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unsigned irq_base)
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{
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int i;
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ramips_intc_base = ioremap_nocache(intc_base, PAGE_SIZE);
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ramips_intc_irq_base = irq_base;
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/* disable all interrupts */
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ramips_intc_wr(~0, INTC_REG_DISABLE);
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/* route all INTC interrupts to MIPS HW0 interrupt */
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ramips_intc_wr(0, INTC_REG_TYPE);
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for (i = ramips_intc_irq_base;
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i < ramips_intc_irq_base + INTC_IRQ_COUNT; i++) {
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set_irq_chip_and_handler(i, &ramips_intc_irq_chip,
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handle_level_irq);
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}
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setup_irq(irq, &ramips_intc_irqaction);
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ramips_intc_wr(INTC_INT_GLOBAL, INTC_REG_ENABLE);
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}
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u32 ramips_intc_get_status(void)
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{
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return ramips_intc_rr(INTC_REG_STATUS0);
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}
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