mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-25 17:51:33 +02:00
298 lines
8.6 KiB
C
298 lines
8.6 KiB
C
/*
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* Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
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* JZ74xx platform GPIO support
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/bitops.h>
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#include <asm/mach-jz4740/regs.h>
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#define JZ_GPIO_BASE_A (32*0)
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#define JZ_GPIO_BASE_B (32*1)
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#define JZ_GPIO_BASE_C (32*2)
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#define JZ_GPIO_BASE_D (32*3)
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#define JZ_GPIO_NUM_A 32
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#define JZ_GPIO_NUM_B 32
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#define JZ_GPIO_NUM_C 31
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#define JZ_GPIO_NUM_D 28
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#define JZ_IRQ_GPIO_BASE_A JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_A
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#define JZ_IRQ_GPIO_BASE_B JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_B
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#define JZ_IRQ_GPIO_BASE_C JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_C
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#define JZ_IRQ_GPIO_BASE_D JZ_IRQ_GPIO(0) + JZ_GPIO_BASE_D
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#define JZ_IRQ_GPIO_A(num) (num < JZ_GPIO_NUM_A ? JZ_IRQ_GPIO_BASE_A + num : -EINVAL)
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#define JZ_IRQ_GPIO_B(num) (num < JZ_GPIO_NUM_B ? JZ_IRQ_GPIO_BASE_B + num : -EINVAL)
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#define JZ_IRQ_GPIO_C(num) (num < JZ_GPIO_NUM_C ? JZ_IRQ_GPIO_BASE_C + num : -EINVAL)
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#define JZ_IRQ_GPIO_D(num) (num < JZ_GPIO_NUM_D ? JZ_IRQ_GPIO_BASE_D + num : -EINVAL)
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#define CHIP_TO_REG(chip, reg) (jz_gpio_base + (((chip)->base) << 3) + reg)
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#define CHIP_TO_PIN_REG(chip) CHIP_TO_REG(chip, 0x00)
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#define CHIP_TO_DATA_REG(chip) CHIP_TO_REG(chip, 0x10)
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#define CHIP_TO_DATA_SET_REG(chip) CHIP_TO_REG(chip, 0x14)
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#define CHIP_TO_DATA_CLEAR_REG(chip) CHIP_TO_REG(chip, 0x18)
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#define CHIP_TO_PULL_REG(chip) CHIP_TO_REG(chip, 0x30)
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#define CHIP_TO_PULL_SET_REG(chip) CHIP_TO_REG(chip, 0x34)
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#define CHIP_TO_PULL_CLEAR_REG(chip) CHIP_TO_REG(chip, 0x38)
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#define CHIP_TO_DATA_SELECT_REG(chip) CHIP_TO_REG(chip, 0x50)
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#define CHIP_TO_DATA_SELECT_SET_REG(chip) CHIP_TO_REG(chip, 0x54)
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#define CHIP_TO_DATA_SELECT_CLEAR_REG(chip) CHIP_TO_REG(chip, 0x58)
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#define CHIP_TO_DATA_DIRECION_REG(chip) CHIP_TO_REG(chip, 0x60)
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#define CHIP_TO_DATA_DIRECTION_SET_REG(chip) CHIP_TO_REG(chip, 0x64)
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#define CHIP_TO_DATA_DIRECTION_CLEAR_REG(chip) CHIP_TO_REG(chip, 0x68)
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#define GPIO_TO_REG(gpio, reg) (jz_gpio_base + ((gpio >> 5) << 8) + reg)
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#define GPIO_TO_PULL_REG(gpio) GPIO_TO_REG(gpio, 0x30)
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#define GPIO_TO_PULL_SET_REG(gpio) GPIO_TO_REG(gpio, 0x34)
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#define GPIO_TO_PULL_CLEAR_REG(gpio) GPIO_TO_REG(gpio, 0x38)
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static void __iomem *jz_gpio_base;
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static spinlock_t jz_gpio_lock;
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struct jz_gpio_chip {
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unsigned int irq_base;
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struct gpio_chip gpio_chip;
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struct irq_chip irq_chip;
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};
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void jz_gpio_enable_pullup(unsigned gpio)
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{
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writel(BIT(gpio & 0x1f), GPIO_TO_PULL_CLEAR_REG(gpio));
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}
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EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
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void jz_gpio_disable_pullup(unsigned gpio)
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{
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writel(BIT(gpio & 0x1f), GPIO_TO_PULL_SET_REG(gpio));
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}
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EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
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void jz_gpio_set_function(unsigned gpio, unsigned function)
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{
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}
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EXPORT_SYMBOL_GPL(jz_gpio_set_function);
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static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
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{
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return !!(readl(CHIP_TO_PIN_REG(chip)) & BIT(gpio));
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}
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static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
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{
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uint32_t __iomem *reg = CHIP_TO_DATA_SET_REG(chip) + ((!value) << 2);
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writel(BIT(gpio), reg);
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}
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static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
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{
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writel(BIT(gpio), CHIP_TO_DATA_DIRECTION_SET_REG(chip));
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jz_gpio_set_value(chip, gpio, value);
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return 0;
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}
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static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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{
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writel(BIT(gpio), CHIP_TO_DATA_DIRECTION_CLEAR_REG(chip));
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return 0;
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}
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#define IRQ_TO_GPIO(irq) (irq - JZ_IRQ_GPIO(0))
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#define IRQ_TO_BIT(irq) BIT(IRQ_TO_GPIO(irq) & 0x1f)
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#define IRQ_TO_REG(irq, reg) GPIO_TO_REG(IRQ_TO_GPIO(irq), reg)
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#define IRQ_TO_MASK_REG(irq) IRQ_TO_REG(irq, 0x20)
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#define IRQ_TO_MASK_SET_REG(irq) IRQ_TO_REG(irq, 0x24)
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#define IRQ_TO_MASK_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x28)
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#define IRQ_TO_SELECT_REG(irq) IRQ_TO_REG(irq, 0x50)
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#define IRQ_TO_SELECT_SET_REG(irq) IRQ_TO_REG(irq, 0x54)
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#define IRQ_TO_SELECT_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x58)
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#define IRQ_TO_DIRECTION_REG(irq) IRQ_TO_REG(irq, 0x60)
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#define IRQ_TO_DIRECTION_SET_REG(irq) IRQ_TO_REG(irq, 0x64)
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#define IRQ_TO_DIRECTION_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x68)
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#define IRQ_TO_TRIGGER_REG(irq) IRQ_TO_REG(irq, 0x70)
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#define IRQ_TO_TRIGGER_SET_REG(irq) IRQ_TO_REG(irq, 0x74)
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#define IRQ_TO_TRIGGER_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x78)
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#define IRQ_TO_FLAG_REG(irq) IRQ_TO_REG(irq, 0x80)
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#define IRQ_TO_FLAG_CLEAR_REG(irq) IRQ_TO_REG(irq, 0x14)
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static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
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{
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uint32_t flag;
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unsigned int gpio_irq;
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unsigned int gpio_bank;
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gpio_bank = IRQ_GPIO0 - irq;
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flag = readl(jz_gpio_base + (gpio_bank << 8) + 0x80);
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gpio_irq = ffs(flag);
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gpio_irq += (gpio_bank << 5) + JZ_IRQ_GPIO(0) - 1;
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generic_handle_irq(gpio_irq);
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};
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/* TODO: Check if function is gpio */
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static unsigned int jz_gpio_irq_startup(unsigned int irq)
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{
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writel(IRQ_TO_BIT(irq), IRQ_TO_SELECT_SET_REG(irq));
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spin_lock(&jz_gpio_lock);
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writel(IRQ_TO_BIT(irq), IRQ_TO_MASK_CLEAR_REG(irq));
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spin_unlock(&jz_gpio_lock);
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return 0;
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}
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static void jz_gpio_irq_shutdown(unsigned int irq)
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{
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spin_lock(&jz_gpio_lock);
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writel(IRQ_TO_BIT(irq), IRQ_TO_MASK_SET_REG(irq));
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spin_unlock(&jz_gpio_lock);
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/* Set direction to input */
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writel(IRQ_TO_BIT(irq), IRQ_TO_DIRECTION_CLEAR_REG(irq));
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writel(IRQ_TO_BIT(irq), IRQ_TO_SELECT_CLEAR_REG(irq));
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}
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static void jz_gpio_irq_mask(unsigned int irq)
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{
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writel(IRQ_TO_BIT(irq), IRQ_TO_MASK_SET_REG(irq));
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};
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static void jz_gpio_irq_unmask(unsigned int irq)
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{
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writel(IRQ_TO_BIT(irq), IRQ_TO_MASK_CLEAR_REG(irq));
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};
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static void jz_gpio_irq_ack(unsigned int irq)
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{
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writel(IRQ_TO_BIT(irq), IRQ_TO_FLAG_CLEAR_REG(irq));
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};
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static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
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{
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uint32_t mask;
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spin_lock(&jz_gpio_lock);
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mask = readl(IRQ_TO_MASK_REG(irq));
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writel(IRQ_TO_BIT(irq), IRQ_TO_MASK_CLEAR_REG(irq));
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switch(flow_type) {
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_EDGE_BOTH:
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writel(IRQ_TO_BIT(irq), IRQ_TO_DIRECTION_SET_REG(irq));
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writel(IRQ_TO_BIT(irq), IRQ_TO_TRIGGER_SET_REG(irq));
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break;
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case IRQ_TYPE_EDGE_FALLING:
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writel(IRQ_TO_BIT(irq), IRQ_TO_DIRECTION_CLEAR_REG(irq));
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writel(IRQ_TO_BIT(irq), IRQ_TO_TRIGGER_SET_REG(irq));
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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writel(IRQ_TO_BIT(irq), IRQ_TO_DIRECTION_SET_REG(irq));
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writel(IRQ_TO_BIT(irq), IRQ_TO_TRIGGER_CLEAR_REG(irq));
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break;
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case IRQ_TYPE_LEVEL_LOW:
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writel(IRQ_TO_BIT(irq), IRQ_TO_DIRECTION_CLEAR_REG(irq));
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writel(IRQ_TO_BIT(irq), IRQ_TO_TRIGGER_CLEAR_REG(irq));
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break;
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default:
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return -EINVAL;
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}
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writel(mask, IRQ_TO_MASK_SET_REG(irq));
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spin_unlock(&jz_gpio_lock);
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return 0;
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}
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int gpio_to_irq(unsigned gpio)
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{
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return JZ_IRQ_GPIO(0) + gpio;
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}
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EXPORT_SYMBOL_GPL(gpio_to_irq);
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int irq_to_gpio(unsigned gpio)
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{
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return IRQ_TO_GPIO(gpio);
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}
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EXPORT_SYMBOL_GPL(irq_to_gpio);
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#define JZ_GPIO_CHIP(_bank) { \
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.irq_base = JZ_IRQ_GPIO_BASE_ ## _bank, \
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.gpio_chip = { \
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.label = "Bank " # _bank, \
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.owner = THIS_MODULE, \
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.set = jz_gpio_set_value, \
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.get = jz_gpio_get_value, \
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.direction_output = jz_gpio_direction_output, \
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.direction_input = jz_gpio_direction_input, \
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.base = JZ_GPIO_BASE_ ## _bank, \
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.ngpio = JZ_GPIO_NUM_ ## _bank, \
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}, \
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.irq_chip = { \
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.name = "GPIO Bank " # _bank, \
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.mask = jz_gpio_irq_mask, \
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.unmask = jz_gpio_irq_unmask, \
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.ack = jz_gpio_irq_ack, \
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.startup = jz_gpio_irq_startup, \
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.shutdown = jz_gpio_irq_shutdown, \
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.set_type = jz_gpio_irq_set_type, \
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}, \
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}
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static struct jz_gpio_chip jz_gpio_chips[] = {
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JZ_GPIO_CHIP(A),
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JZ_GPIO_CHIP(B),
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JZ_GPIO_CHIP(C),
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JZ_GPIO_CHIP(D),
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};
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__init int jz_gpiolib_init(void)
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{
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struct jz_gpio_chip *chip = jz_gpio_chips;
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int i, irq;
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jz_gpio_base = ioremap(0x10010000, 0x400);
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for (i = 0; i < ARRAY_SIZE(jz_gpio_chips); ++i, ++chip) {
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gpiochip_add(&chip->gpio_chip);
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enable_irq(JZ_IRQ_INTC_GPIO(i));
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set_irq_chained_handler(JZ_IRQ_INTC_GPIO(i), jz_gpio_irq_demux_handler);
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for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio;
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++irq)
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set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq);
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}
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printk("JZ GPIO initalized\n");
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return 0;
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}
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