mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-10 08:31:53 +02:00
e2b4e2abff
git-svn-id: svn://svn.openwrt.org/openwrt/trunk/openwrt@1132 3c298f89-4303-0410-b956-a3cf2f4a3e73
243 lines
6.1 KiB
Diff
243 lines
6.1 KiB
Diff
diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
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--- linux.old/arch/mips/mm/c-r4k.c 2005-06-01 18:42:44.000000000 +0200
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+++ linux.dev/arch/mips/mm/c-r4k.c 2005-06-01 18:49:07.000000000 +0200
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@@ -14,6 +14,12 @@
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#include <linux/mm.h>
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#include <linux/bitops.h>
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+#ifdef CONFIG_BCM4710
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+#include "../bcm947xx/include/typedefs.h"
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+#include "../bcm947xx/include/sbconfig.h"
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+#include <asm/paccess.h>
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+#endif
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+
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#include <asm/bcache.h>
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#include <asm/bootinfo.h>
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#include <asm/cacheops.h>
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@@ -390,6 +396,11 @@
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addr = start & ~(dc_lsize - 1);
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aend = (end - 1) & ~(dc_lsize - 1);
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+#ifdef CONFIG_BCM4710
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+ BCM4710_FILL_TLB(addr);
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+ BCM4710_FILL_TLB(aend);
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+#endif
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+
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while (1) {
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/* Hit_Writeback_Inv_D */
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protected_writeback_dcache_line(addr);
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@@ -405,6 +416,10 @@
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else {
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addr = start & ~(ic_lsize - 1);
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aend = (end - 1) & ~(ic_lsize - 1);
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+#ifdef CONFIG_BCM4710
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+ BCM4710_FILL_TLB(addr);
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+ BCM4710_FILL_TLB(aend);
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+#endif
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while (1) {
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/* Hit_Invalidate_I */
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protected_flush_icache_line(addr);
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@@ -487,6 +502,10 @@
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a = addr & ~(sc_lsize - 1);
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end = (addr + size - 1) & ~(sc_lsize - 1);
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+#ifdef CONFIG_BCM4710
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+ BCM4710_FILL_TLB(a);
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+ BCM4710_FILL_TLB(end);
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+#endif
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while (1) {
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flush_scache_line(a); /* Hit_Writeback_Inv_SD */
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if (a == end)
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@@ -509,6 +528,10 @@
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R4600_HIT_CACHEOP_WAR_IMPL;
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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+#ifdef CONFIG_BCM4710
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+ BCM4710_FILL_TLB(a);
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+ BCM4710_FILL_TLB(end);
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+#endif
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while (1) {
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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if (a == end)
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@@ -537,6 +560,10 @@
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a = addr & ~(sc_lsize - 1);
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end = (addr + size - 1) & ~(sc_lsize - 1);
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+#ifdef CONFIG_BCM4710
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+ BCM4710_FILL_TLB(a);
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+ BCM4710_FILL_TLB(end);
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+#endif
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while (1) {
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flush_scache_line(a); /* Hit_Writeback_Inv_SD */
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if (a == end)
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@@ -576,6 +603,10 @@
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unsigned long ic_lsize = current_cpu_data.icache.linesz;
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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+#ifdef CONFIG_BCM4710
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+ BCM4710_PROTECTED_FILL_TLB(addr);
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+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
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+#endif
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R4600_HIT_CACHEOP_WAR_IMPL;
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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protected_flush_icache_line(addr & ~(ic_lsize - 1));
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diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
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--- linux.old/include/asm-mips/r4kcache.h 2005-06-01 18:42:43.000000000 +0200
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+++ linux.dev/include/asm-mips/r4kcache.h 2005-06-01 19:07:11.000000000 +0200
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@@ -15,6 +15,25 @@
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#include <asm/asm.h>
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#include <asm/cacheops.h>
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+#ifdef CONFIG_BCM4710
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+#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
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+
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+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
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+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
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+
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+#define cache_op(op,addr) \
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+ BCM4710_DUMMY_RREG(); \
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+ __asm__ __volatile__( \
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+ " .set noreorder \n" \
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+ " .set mips3\n\t \n" \
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+ " cache %0, %1 \n" \
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+ " .set mips0 \n" \
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+ " .set reorder" \
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+ : \
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+ : "i" (op), "m" (*(unsigned char *)(addr)))
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+
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+#else
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+
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#define cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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@@ -24,6 +43,8 @@
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" .set reorder" \
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: \
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: "i" (op), "m" (*(unsigned char *)(addr)))
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+#endif
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+
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static inline void flush_icache_line_indexed(unsigned long addr)
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{
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@@ -32,6 +53,9 @@
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static inline void flush_dcache_line_indexed(unsigned long addr)
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{
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+#ifdef CONFIG_BCM4710
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+ BCM4710_DUMMY_RREG();
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+#endif
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cache_op(Index_Writeback_Inv_D, addr);
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}
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@@ -47,6 +71,10 @@
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static inline void flush_dcache_line(unsigned long addr)
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{
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+
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+#ifdef CONFIG_BCM4710
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+ BCM4710_DUMMY_RREG();
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+#endif
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cache_op(Hit_Writeback_Inv_D, addr);
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}
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@@ -91,6 +119,9 @@
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*/
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static inline void protected_writeback_dcache_line(unsigned long addr)
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{
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+#ifdef CONFIG_BCM4710
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+ BCM4710_DUMMY_RREG();
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+#endif
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__asm__ __volatile__(
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".set noreorder\n\t"
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".set mips3\n"
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@@ -148,8 +179,12 @@
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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- for (addr = start; addr < end; addr += 0x200)
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+ for (addr = start; addr < end; addr += 0x200) {
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+#ifdef CONFIG_BCM4710
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+ BCM4710_DUMMY_RREG();
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+#endif
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cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
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+ }
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}
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static inline void blast_dcache16_page(unsigned long page)
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@@ -158,6 +193,9 @@
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unsigned long end = start + PAGE_SIZE;
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do {
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+#ifdef CONFIG_BCM4710
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+ BCM4710_DUMMY_RREG();
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+#endif
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cache16_unroll32(start,Hit_Writeback_Inv_D);
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start += 0x200;
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} while (start < end);
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@@ -173,8 +211,12 @@
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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- for (addr = start; addr < end; addr += 0x200)
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+ for (addr = start; addr < end; addr += 0x200) {
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+#ifdef CONFIG_BCM4710
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+ BCM4710_DUMMY_RREG();
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+#endif
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cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
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+ }
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}
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static inline void blast_icache16(void)
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@@ -196,7 +238,13 @@
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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+#ifdef CONFIG_BCM4710
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+ BCM4710_FILL_TLB(start);
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+#endif
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do {
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+#ifdef CONFIG_BCM4710
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+ BCM4710_DUMMY_RREG();
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+#endif
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cache16_unroll32(start,Hit_Invalidate_I);
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start += 0x200;
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} while (start < end);
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@@ -291,8 +339,12 @@
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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- for (addr = start; addr < end; addr += 0x400)
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+ for (addr = start; addr < end; addr += 0x400) {
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+#ifdef CONFIG_BCM4710
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+ BCM4710_DUMMY_RREG();
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+#endif
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cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
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+ }
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}
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static inline void blast_dcache32_page(unsigned long page)
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@@ -300,7 +352,13 @@
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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+#ifdef CONFIG_BCM4710
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+ __asm__ __volatile__("nop;nop;nop;nop");
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+#endif
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do {
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+#ifdef CONFIG_BCM4710
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+ BCM4710_DUMMY_RREG();
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+#endif
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cache32_unroll32(start,Hit_Writeback_Inv_D);
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start += 0x400;
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} while (start < end);
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@@ -339,6 +397,9 @@
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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+#ifdef CONFIG_BCM4710
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+ BCM4710_FILL_TLB(start);
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+#endif
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do {
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cache32_unroll32(start,Hit_Invalidate_I);
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start += 0x400;
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