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c2ffdb04c4
This patch cleans up the include directory, as they were from vendors 2.4 GPL source. Now only what's used is there. Signed-off-by: Scott Nicholas <scott.nicholas@scottn.us> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@25175 3c298f89-4303-0410-b956-a3cf2f4a3e73
140 lines
3.8 KiB
C
140 lines
3.8 KiB
C
/************************************************************************
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*
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* Copyright (c) 2005
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* Infineon Technologies AG
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* St. Martin Strasse 53; 81669 Muenchen; Germany
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*
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************************************************************************/
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#ifndef __ADM8668_H__
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#define __ADM8668_H__
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#define SYS_CLOCK 175000000
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/*======================= Physical Memory Map ============================*/
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#define ADM8668_SDRAM_BASE 0
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#define ADM8668_SMEM1_BASE 0x10000000
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#define ADM8668_MPMC_BASE 0x11000000
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#define ADM8668_USB_BASE 0x11200000
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#define ADM8668_CONFIG_BASE 0x11400000
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#define ADM8668_WAN_BASE 0x11600000
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#define ADM8668_WLAN_BASE 0x11800000
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#define ADM8668_LAN_BASE 0x11A00000
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#define ADM8668_INTC_BASE 0x1E000000
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#define ADM8668_TMR_BASE 0x1E200000
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#define ADM8668_UART0_BASE 0x1E400000
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#define ADM8668_SMEM0_BASE 0x1FC00000
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#define ADM8668_NAND_BASE 0x1FFFFF00
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#define PCICFG_BASE 0x12200000
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#define PCIDAT_BASE 0x12400000
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/** onboard uart **/
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#define ADM8668_UARTCLK_FREQ 62500000
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/* registers */
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#define UART_DR_REG 0x00
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#define UART_RSR_REG 0x04
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#define UART_CR_REG 0x14
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#define UART_FR_REG 0x18
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#define UART_IIR_REG 0x1C
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/* rsr reg */
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#define UART_FRAMING_ERR 0x01
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#define UART_PARITY_ERR 0x02
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#define UART_BREAK_ERR 0x04
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#define UART_OVERRUN_ERR 0x08
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#define UART_RX_STATUS_MASK 0x0F
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/* cr reg */
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#define UART_RX_INT_EN 0x10
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#define UART_TX_INT_EN 0x20
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#define UART_RX_TIMEOUT_INT_EN 0x40
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/* fr reg */
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#define UART_RX_FIFO_EMPTY 0x10
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#define UART_TX_FIFO_FULL 0x20
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/* iir reg */
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#define UART_RX_INT 0x02
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#define UART_TX_INT 0x04
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#define UART_RX_TIMEOUT_INT 0x08
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/* interrupt controller */
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#define IRQ_STATUS_REG 0x00 /* Read */
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#define IRQ_ENABLE_REG 0x08 /* Read/Write */
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#define IRQ_DISABLE_REG 0x0C /* Write */
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/* interrupt levels */
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#define INT_LVL_SWI 1
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#define INT_LVL_COMMS_RX 2
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#define INT_LVL_COMMS_TX 3
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#define INT_LVL_TIMERINT0 4
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#define INT_LVL_TIMERINT1 5
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#define INT_LVL_UART0 6
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#define INT_LVL_LAN 7
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#define INT_LVL_WAN 8
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#define INT_LVL_WLAN 9
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#define INT_LVL_GPIO 10
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#define INT_LVL_IDE 11
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#define INT_LVL_PCI2 12
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#define INT_LVL_PCI1 13
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#define INT_LVL_PCI0 14
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#define INT_LVL_USB 15
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#define INT_LVL_MAX INT_LVL_USB
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/* register access macros */
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#define ADM8668_INTC_REG(_reg) \
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(*((volatile unsigned long *)(KSEG1ADDR(ADM8668_INTC_BASE + (_reg)))))
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#define ADM8668_LAN_REG(_reg) \
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(*((volatile unsigned int *)(KSEG1ADDR(ADM8668_LAN_BASE + (_reg)))))
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#define ADM8668_WAN_REG(_reg) \
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(*((volatile unsigned int *)(KSEG1ADDR(ADM8668_WAN_BASE + (_reg)))))
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#define ADM8668_WLAN_REG(_reg) \
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(*((volatile unsigned int *)(KSEG1ADDR(ADM8668_WLAN_BASE + (_reg)))))
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#define ADM8668_CONFIG_REG(_reg) \
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(*((volatile unsigned int *)(KSEG1ADDR(ADM8668_CONFIG_BASE + (_reg)))))
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/* lan registers */
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#define NETCSR6 0x30
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#define NETCSR7 0x38
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#define NETCSR37 0xF8
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/* known/used CPU configuration registers */
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#define ADM8668_CR0 0x00
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#define ADM8668_CR1 0x04
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#define ADM8668_CR3 0x0C
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/** For GPIO control **/
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#define GPIO_REG 0x5C /* on WLAN */
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#define CRGPIO_REG 0x20 /* on CPU */
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#define GPIO0_OUTPUT_ENABLE 0x1000
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#define GPIO1_OUTPUT_ENABLE 0x2000
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#define GPIO2_OUTPUT_ENABLE 0x4000
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#define GPIO_OUTPUT_ENABLE_ALL 0x7000
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#define GPIO0_OUTPUT_1 0x40
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#define GPIO1_OUTPUT_1 0x80
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#define GPIO2_OUTPUT_1 0x100
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#define GPIO0_INPUT_1 0x1
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#define GPIO1_INPUT_1 0x2
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#define GPIO2_INPUT_1 0x4
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#define GPIO_SET_HI(num) \
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ADM8668_WLAN_REG(GPIO_REG) |= (1 << (6 + num))
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#define GPIO_SET_LOW(num) \
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ADM8668_WLAN_REG(GPIO_REG) &= ~(1 << (6 + num))
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#define GPIO_TOGGLE(num) \
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ADM8668_WLAN_REG(GPIO_REG) ^= (1 << (6 + num))
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#define CRGPIO_SET_HI(num) \
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ADM8668_CONFIG_REG(CRGPIO_REG) |= (1 << (6 + num))
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#define CRGPIO_SET_LOW(num) \
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ADM8668_CONFIG_REG(CRGPIO_REG) &= ~(1 << (6 + num))
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#define CRGPIO_TOGGLE(num) \
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ADM8668_CONFIG_REG(CRGPIO_REG) ^= (1 << (6 + num))
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#endif /* __ADM8668_H__ */
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